


 ;	SNES.txt
 ;	
 ;
 ;	Written by illegal eagle for vSNES 2.00; last update: 2004-10-04 00:40
 ;	Feel free to use this info for anything you want, but don't expect it to be perfect.
 ;	Use no line-wrap and a tabulator width of 8 chars per tab (as in Notepad) for viewing.

 ;	The registers are sorted by index and are grouped by function (with some exceptions).
 ;	The 1st column contains the addresses of the memory-mapped registers, the SPC700
 ;	registers and the DSP registers.
 ;	The 2nd column contains the type of the memory-mapped registers:
 ;
 ;		r  =  read-only
 ;		 w = write-only
 ;		r? =  readable, might be writeable
 ;		?w = writeable, might be  readable
 ;		rw = readable and writeable
 ;
 ;	The 3rd column contains the number of bits.
 ;	The 4th column contains the names of the registers; some docs use a different set.
 ;	The 5th column contains comments to the registers; bits are in reverse order and are
 ;	named D31..D0.  The comments are just a short reference and not a full technical doc.
 ;
 ;	The write-only registers (or data ports) don't show the value you would get
 ;	by reading, but show the internal status (or the next value to read/overwrite).
 ;
 ;	If an internal value is formed by several registers then it's displayed first.

 ;	The DSP registers are stored in the RAM bytes of the DSP.  Therefore they're
 ;	always readable and writeable, but some status registers are set by the DSP.



[CPU]
						; [GTE-65sc816 REGISTERS]
		16	C			; Accumulator (B SHL 8 plus A)
		 8	A			; accumulator (low)
		 8	B			; accumulator (high)
		16	X			; index or general purpose register
		16	Y			; index or general purpose register
		 8	P			; NVMXDIZC or NV1BDIZC bits (Processor Status flags)
		24	DBptr			; Data Bank pointer (24-bit effective data address)
		16	D			; Direct Page pointer (Direct Page address in bank 0)
		16	S			; Stack Pointer (stack address in bank 0 if E=0, else bank 1)
		24	PBPC			; effective Program address (PB SHL 16 plus PC)
		 8	PB			; Program Bank
		16	PC			; Program Counter
		 8	DB			; Data Bank (bits 23..16 of the 24-bit effective Data address)

						; [PROCESSOR STATUS FLAGS]
		 1	C			; Carry
		 1	Z			; Result Zero
		 1	I			; IRQ Disable
		 1	D			; Decimal Mode: decimal (1), binary (0)
		 1	X			; Index registers: 8-bit (1), 16-bit (0)
		 1	M			; Memory/Accumulator: 8-bit (1), 16 bit (0)
		 1	V			; Overflow
		 1	N			; Negative
		 1	E			; 6502 Emulation (hidden); can be exchanged with C
		 1	B			; BRK (hidden if E=0); replaces X while E=1


						; [INTERNAL VARIABLES]
		 1	curNMI			; if in NMI (1) or not (0)
		 8	CycpL			; cycles per scanline
		 8	curCyc			; cycles left in scanline
		 8	CycpHB			; cycles per hblank


						; [MEMORY-MAPPED REGISTERS]
 4016	rw	 8	JoySer0			; famicom-style data port for ctrl 1 (and maybe 3)
 4017	rw	 8	JoySer1			; famicom-style data port for ctrl 2 (and maybe 4)

 4200	 w	 8	NMITimEn		; flags: NMI (D7), V-IRQ (D5), H-IRQ (D4), JOY (D0)
 4201	 w	 8	wrIO			; programmable I/O port (OUT port)
 4202	 w	 8	wrMpyA			; multiplier
 4203	 w	 8	wrMpyB			; multiplicant
		16	wrDiv			; divident
 4204	 w	 8	wrDivL			; divident (low)
 4205	 w	 8	wrDivH			; divident (high)
 4206	 w	 8	wrDivB			; divisor
		 9	hTime			; H-IRQ xpos
 4207	 w	 8	hTimeL			; H-IRQ xpos (bit 0..7)
 4208	 w	 1	hTimeH			; H-IRQ xpos (bit 8)
		 9	vTime			; V-IRQ ypos
 4209	 w	 8	vTimeL			; V-IRQ ypos (bit 0..7)
 420A	 w	 1	vTimeH			; V-IRQ ypos (bit 8)
 420B	 w	 8	mDMAEn			; status flags: DMA channels
 420C	 w	 8	hDMAEn			; status flags: H-DMA channels
 420D	 w	 1	MemSel			; speed for WRAM starting at 80:8000: 3.58 MHz (1), 2.68 MHz (0)

 4210	r	 8	rdNMI			; NMI flag by V-Blank (D7) (reset by read), 5A22 version (D3..D0)
 4211	r?	 8	TimeUp			; 'H-IRQ or V-IRQ' flag (D7); becomes zero after reading
 4212	r?	 8	HVBJoy			; V-Blank (D7), H-Blank (D6), JOY Reading (D0)
 4213	r	 8	rdIO			; programmable I/O port (IN port)
		16	rdDiv			; quotient of divide result
 4214	r	 8	rdDivL			; quotient of divide result (low)
 4215	r	 8	rdDivH			; quotient of divide result (high)
		16	rdMpy			; product of mult. result or remainder of div. result
 4216	r	 8	rdMpyL			; product of mult. result or remainder of div. result (low)
 4217	r	 8	rdMpyH			; product of mult. result or remainder of div. result (high)

 4218	r	 8	Joy1L			; JOY ctrl 1 (D7..D4): X, Y, Top Right, Top Left
 4219	r	 8	Joy1H			; JOY ctrl 1 (D7..D0): A, B, Select, Start, Up, Down, Left, Right
 421A	r	 8	Joy2L			; JOY ctrl 2 (D7..D4): X, Y, Top Right, Top Left
 421B	r	 8	Joy2H			; JOY ctrl 2 (D7..D0): A, B, Select, Start, Up, Down, Left, Right
 421C	r	 8	Joy3L			; JOY ctrl 3 (D7..D4): X, Y, Top Right, Top Left
 421D	r	 8	Joy3H			; JOY ctrl 3 (D7..D0): A, B, Select, Start, Up, Down, Left, Right
 421E	r	 8	Joy4L			; JOY ctrl 4 (D7..D4): X, Y, Top Right, Top Left
 421F	r	 8	Joy4H			; JOY ctrl 4 (D7..D0): A, B, Select, Start, Up, Down, Left, Right



[DMA]
						; [INFO FOR CHANNELS 0..7]
 4300	 w	 8	dma0Param		; DMA transfer parameters
 4310	 w	 8	dma1Param
 4320	 w	 8	dma2Param		; D7: Bus transfer direction; A to B (0) or B to A (1)
 4330	 w	 8	dma3Param		; D6: H-DMA addressing mode; absolute (0) or indirect (1)
 4340	 w	 8	dma4Param		; D4: inc/dec setting for D3=0: automatic inc. (0) or dec. (1)
 4350	 w	 8	dma5Param		; D3: fixed address (1) or automatic inc/dec (0) for A-Bus
 4360	 w	 8	dma6Param		; D2..D0: DMA transfer word select
 4370	 w	 8	dma7Param

 4301	 w	 8	dma0B			; B-Bus address
 4311	 w	 8	dma1B			; address of the destination register will be 21??h
 4321	 w	 8	dma2B
 4331	 w	 8	dma3B
 4341	 w	 8	dma4B
 4351	 w	 8	dma5B
 4361	 w	 8	dma6B
 4371	 w	 8	dma7B

		16	dma0A1			; A1 table address
		16	dma1A1
		16	dma2A1
		16	dma3A1
		16	dma4A1
		16	dma5A1
		16	dma6A1
		16	dma7A1

 4302	 w	 8	dma0A1L			; A1 table address (low)
 4312	 w	 8	dma1A1L
 4322	 w	 8	dma2A1L
 4332	 w	 8	dma3A1L
 4342	 w	 8	dma4A1L
 4352	 w	 8	dma5A1L
 4362	 w	 8	dma6A1L
 4372	 w	 8	dma7A1L

 4303	 w	 8	dma0A1H			; A1 table address (high)
 4313	 w	 8	dma1A1H
 4323	 w	 8	dma2A1H
 4333	 w	 8	dma3A1H
 4343	 w	 8	dma4A1H
 4353	 w	 8	dma5A1H
 4363	 w	 8	dma6A1H
 4373	 w	 8	dma7A1H

 4304	 w	 8	dma0ABank		; A-table bank
 4314	 w	 8	dma1ABank
 4324	 w	 8	dma2ABank
 4334	 w	 8	dma3ABank
 4344	 w	 8	dma4ABank
 4354	 w	 8	dma5ABank
 4364	 w	 8	dma6ABank
 4374	 w	 8	dma7ABank

		16	dma0Data		; data address for H-DMA or byte count for DMA
		16	dma1Data		; 'Data' means extra data for general purpose
		16	dma2Data
		16	dma3Data
		16	dma4Data
		16	dma5Data
		16	dma6Data
		16	dma7Data

 4305	 w	 8	dma0DataL		; data address for H-DMA or byte count for DMA (low)
 4315	 w	 8	dma1DataL		; 'Data' means extra data for general purpose
 4325	 w	 8	dma2DataL
 4335	 w	 8	dma3DataL
 4345	 w	 8	dma4DataL
 4355	 w	 8	dma5DataL
 4365	 w	 8	dma6DataL
 4375	 w	 8	dma7DataL

 4306	 w	 8	dma0DataH		; data address for H-DMA or byte count for DMA (high)
 4316	 w	 8	dma1DataH		; 'Data' means extra data for general purpose
 4326	 w	 8	dma2DataH
 4336	 w	 8	dma3DataH
 4346	 w	 8	dma4DataH
 4356	 w	 8	dma5DataH
 4366	 w	 8	dma6DataH
 4376	 w	 8	dma7DataH

 4307	 w	 8	dma0HBank		; data bank for H-DMA
 4317	 w	 8	dma1HBank
 4327	 w	 8	dma2HBank
 4337	 w	 8	dma3HBank
 4347	 w	 8	dma4HBank
 4357	 w	 8	dma5HBank
 4367	 w	 8	dma6HBank
 4377	 w	 8	dma7HBank

		16	dma0A2			; A2 table address
		16	dma1A2
		16	dma2A2
		16	dma3A2
		16	dma4A2
		16	dma5A2
		16	dma6A2
		16	dma7A2

 4308	?w	 8	dma0A2L			; A2 table address (low)
 4318	?w	 8	dma1A2L			; (might be readable)
 4328	?w	 8	dma2A2L
 4338	?w	 8	dma3A2L
 4348	?w	 8	dma4A2L
 4358	?w	 8	dma5A2L
 4368	?w	 8	dma6A2L
 4378	?w	 8	dma7A2L

 4309	?w	 8	dma0A2H			; A2 table address (high)
 4319	?w	 8	dma1A2H			; (might be readable)
 4329	?w	 8	dma2A2H
 4339	?w	 8	dma3A2H
 4349	?w	 8	dma4A2H
 4359	?w	 8	dma5A2H
 4369	?w	 8	dma6A2H
 4379	?w	 8	dma7A2H

 430A	?w	 8	dma0HLine		; number of line to be transferred by H-DMA
 431A	?w	 8	dma1HLine		; (probably readable)
 432A	?w	 8	dma2HLine
 433A	?w	 8	dma3HLine		; Continue (D7), value (D6..D0)
 434A	?w	 8	dma4HLine
 435A	?w	 8	dma5HLine
 436A	?w	 8	dma6HLine
 437A	?w	 8	dma7HLine



[PPU]
 2100	 w	 8	IniDisp			; forced blanking (D7), screen brightness (D3..D0)

 2101	 w	 8	OBJSel			; OBJ size (D7..D5), OBJ name (D4..D3), OBJ name base (D1..D0)
		 9	OAMAdd			; OAM address
 2102	 w	 8	OAMAddL			; OAM address (bit 0..7)
 2103	 w	 8	OAMAddH			; OAM priority rotation (D7), bit 8 of OAM address (D0)
 2104	 w	 8	OAMData			; data port for writing into OAM

 2105	 w	 8	BGMode			; BG4..BG1 char size (D7..D4), BG3-p1 on top (D3), BG mode (D2..D0)
 2106	 w	 8	Mosaic			; mosaic size (D7..D4), BG4..BG1 flags (D3..D0)
 2107	 w	 7	BG1SC			; BG1 tilemap: address (D6..D2), height=64 (D1), width=64 (D0)
 2108	 w	 7	BG2SC			; BG2 tilemap: address (D6..D2), height=64 (D1), width=64 (D0)
 2109	 w	 7	BG3SC			; BG3 tilemap: address (D6..D2), height=64 (D1), width=64 (D0)
 210A	 w	 7	BG4SC			; BG4 tilemap: address (D6..D2), height=64 (D1), width=64 (D0)
 210B	 w	 7	BG12NBA			; name base address: BG2 (D6..D4), BG1 (D2..D0)
 210C	 w	 7	BG34NBA			; name base address: BG4 (D6..D4), BG3 (D2..D0)
 210D	 w	13	BG1hOfs			; BG1 H-Offset (D9..D0; D12..D0 in Mode7)
 210E	 w	13	BG1vOfs			; BG1 V-Offset (D9..D0; D12..D0 in Mode7)
 210F	 w	10	BG2hOfs			; BG2 H-Offset (D9..D0)
 2110	 w	10	BG2vOfs			; BG2 V-Offset (D9..D0)
 2111	 w	10	BG3hOfs			; BG3 H-Offset (D9..D0)
 2112	 w	10	BG3vOfs			; BG3 V-Offset (D9..D0)
 2113	 w	10	BG4hOfs			; BG4 H-Offset (D9..D0)
 2114	 w	10	BG4vOfs			; BG4 V-Offset (D9..D0)

 2115	 w	 8	VMAInc			; incr. at 2118h/2139h or 2119h/213Ah access (D7), sequence mode (D3..D0)
		16	VMAddB			; VRAM address; points to a VRAM byte
		15	VMAdd			; VRAM address; points to a VRAM word
 2116	 w	 8	VMAddL			; VRAM address (bit 7..0)
 2117	 w	 7	VMAddH			; VRAM address (bit 14..8); D15 is not used (VRAM size = 64 KB)
		16	VMData			; data port for writing into VRAM
 2118	 w	 8	VMDataL			; data port for writing into VRAM (low)
 2119	 w	 8	VMDataH			; data port for writing into VRAM (high)

 211A	 w	 8	M7Sel			; screen over setting (D7..D6), screen flip (D1..D0)
 211B	 w	16	M7A			; matrix parameter A (D15..D0)
 211C	 w	16	M7B			; matrix parameter B (D15..D0)
 211D	 w	16	M7C			; matrix parameter C (D15..D0)
 211E	 w	16	M7D			; matrix parameter D (D15..D0)
 211F	 w	13	M7X			; center: x position (D12..D0)
 2120	 w	13	M7Y			; center: y position (D12..D0)

		 9	CGAddB			; CGRAM address; points to CGRAM byte
 2121	 w	 8	CGAdd			; CGRAM address; points to CGRAM word (ie. a palette entry)
 2122	 w	15	CGDataW			; data port for writing into CGRAM (D14..D0)

 2123	 w	 8	W12Sel			; wnd2 on,inv, wnd1 on,inv: BG2 (D7..D4), BG1 (D3..D0)
 2124	 w	 8	W34Sel			; wnd2 on,inv, wnd1 on,inv: BG4 (D7..D4), BG3 (D3..D0)
 2125	 w	 8	WOBJSel			; wnd2 on,inv, wnd1 on,inv: color window (D7..D4), OBJ (D3..D0)
 2126	 w	 8	WH0			; window 1: first pixel (left position)
 2127	 w	 8	WH1			; window 1: last pixel (right position)
 2128	 w	 8	WH2			; window 2: first pixel (left position)
 2129	 w	 8	WH3			; window 2: last pixel (right position)
 212A	 w	 8	WBGLog			; 0..3=OR/AND/XOR/XNOR: BG4..BG1 (D7..D0, 2 bits each)
 212B	 w	 4	WOBJLog			; 0..3=OR/AND/XOR/XNOR: color window (D3..D2), OBJ (D1..D0)
 212C	 w	 5	TM			; OBJ (D4), BG4..BG1 (D3..D0): designation for main screen
 212D	 w	 5	TS			; OBJ (D4), BG4..BG1 (D3..D0): designation for sub screen
 212E	 w	 5	TMW			; OBJ (D4), BG4..BG1 (D3..D0): mask window on main screen
 212F	 w	 5	TSW			; OBJ (D4), BG4..BG1 (D3..D0): mask window on sub screen

 2130	 w	 8	CGSWSel			; D7..D4: main,sub (0..3=all,in,out,off), use SubScr (D1), direct col. (D0)
 2131	 w	 8	CGAdSub			; add/sub mode (D7), 0.5 mode (D6); D5..D0: add/sub on BACK, OBJ, BG4..BG1
 2132	 w	15	ColData			; fixed color constant
		 5	ColRed			; fixed color constant: red
		 5	ColGreen		; fixed color constant: green
		 5	ColBlue			; fixed color constant: blue
 2133	 w	 8	SetIni			; ext. sync (D7), EXTBG (D6); D3..D0: H-512, V-239, OBJ-V x1, interlace

		24	Mpy			; multiplication result
 2134	r?	 8	MpyL			; multiplication result (low)
 2135	r?	 8	MpyM			; multiplication result (mid)
 2136	r?	 8	MpyH			; multiplication result (high)

 2137	r	 8	SLHV			; read access latches H/V-Counter, returned data is meaningless
 2138	r	 8	OAMData			; data port for reading from OAM
		16	VMData			; data port for reading from VRAM
 2139	r	 8	VMDataL			; data port for reading from VRAM (low)
 213A	r	 8	VMDataH			; data port for reading from VRAM (high)
 213B	r	 8	CGDataR			; data port for reading from CGRAM
 213C	r	 9	OPhCt			; output data of H-Counter (D8..D0);  H-Blank = values 256..339
 213D	r	 9	OPvCt			; output data of V-Counter (D8..D0);  V-Blank = values 224..261 or 239..261
 213E	r	 8	Stat77			; Time over (D7), Range over (D6), master/slave (D5), 5C77 version (D3..D0)
 213F	r	 8	Stat78			; field (D7), external latch (D6), PAL mode (D4), 5C78 version (D3..D0)

 2140	rw	 8	APU100			; APU I/O port 0; connects to 00F4h of the SPC700
 2141	rw	 8	APU101			; APU I/O port 1; connects to 00F5h of the SPC700
 2142	rw	 8	APU102			; APU I/O port 2; connects to 00F6h of the SPC700
 2143	rw	 8	APU103			; APU I/O port 3; connects to 00F7h of the SPC700

 2180	rw	 8	WMData			; data port for reading from WRAM and writing into WRAM
		17	WMAdd			; WRAM (RAM) address
 2181	rw	 8	WMAddL			; WRAM (RAM) address (bit 7..0)
 2182	rw	 8	WMAddM			; WRAM (RAM) address (bit 15..8)
 2183	rw	 8	WMAddH			; WRAM (RAM) address (bit 16)



[APU]
						; [SONY-SPC700 REGISTERS]
		16	YA			; Accumulator (Y SHL 8 plus A)
		 8	A			; accumulator (low)
		 8	X			; index or general purpose register
		 8	Y			; index or general purpose register / accumulator (high)
		 8	PSW			; NVP-H-ZC bits (Processor Status Ward flags)
		16	PC			; Program Counter (PCH SHL 8 plus PCL)
		 8	PCL			; program counter (low)
		 8	PCH			; program counter (high)
		 8	DP			; Direct Page pointer
		 8	SP			; Stack Pointer (effective address = 0100h + SP)

						; status flags in PSW:
		 1	C			; Carry
		 1	Z			; Zero
		 1	H			; Half Carry
		 1	D			; Direct Page; Direct Page address = 0000h (0) or 0100h (1)
		 1	V			; Overflow
		 1	N			; Negative

 00F1	 w	 6	spcCtrl			; I/O port clear bits (D5..D4), timer status (D2..D0)
 00F2	rw	 8	spcDRgA			; DSP register address
 00F3	rw	 8	spcDDat			; port for reading or writing DSP register data

 00F4	rw	 8	spcPort0		; port 0; connects to 2140h of the main CPU
 00F5	rw	 8	spcPort1		; port 1; connects to 2141h of the main CPU
 00F6	rw	 8	spcPort2		; port 2; connects to 2142h of the main CPU
 00F7	rw	 8	spcPort3		; port 3; connects to 2143h of the main CPU

 00FA	 w	 8	spcTmLt0		; latch (hit value) for timer0 (8 kHz)
 00FB	 w	 8	spcTmLt1		; latch (hit value) for timer1 (8 kHz)
 00FC	 w	 8	spcTmLt2		; latch (hit value) for timer2 (64 kHz)
 00FD	r	 4	spcTmCt0		; timer0 hit counter (D3..D0); used bits get cleared by reading
 00FE	r	 4	spcTmCt1		; timer1 hit counter (D3..D0); used bits get cleared by reading
 00FF	r	 4	spcTmCt2		; timer2 hit counter (D3..D0); used bits get cleared by reading


						; [SONY-DSP (SFC APU) REGISTERS]
 000C	rw	 8	MVolumeL		; master volume; sign (D7), value (D6..D0) for left
 001C	rw	 8	MVolumeR		; master volume; sign (D7), value (D6..D0) for right
 002C	rw	 8	EVolumeL		; echo volume; sign (D7), value (D6..D0) for left
 003C	rw	 8	EVolumeR		; echo volume; sign (D7), value (D6..D0) for right
 004C	rw	 8	KeyOn			; voice flags: key-on
 005C	rw	 8	KeyOff			; voice flags: key-off
 006C	rw	 8	FLG			; Reset (D7), Mute (D6), Echo (D5), Noice Clock (D4..D0)
 007C	rw	 8	EndX			; voice flags: source end block encountered

 000D	rw	 8	EchoFB			; echo feedback: sign (D7), value (D6..D0)
 002D	rw	 8	PitchMod		; voice flags: pitch modulation  (D7..D1)
 003D	rw	 8	NoiseON			; voice flags: noise
 004D	rw	 8	EchoON			; voice flags: echo
 005D	rw	 8	DIR			; location of the sample directory
 006D	rw	 8	EchoSAddr		; location of the echo waveform directory
 007D	rw	 4	EchoDelay		; echo delay (D3..D0)

 000F	rw	 8	C0			; echo FIR filter coefficients
 001F	rw	 8	C1			; sign (D7), value (D6..D0)
 002F	rw	 8	C2
 003F	rw	 8	C3
 004F	rw	 8	C4
 005F	rw	 8	C5
 006F	rw	 8	C6
 007F	rw	 8	C7

						; [INFO FOR DSP VOICES 0..7]
 0000	rw	 8	V0VolumeL		; volume for left
 0010	rw	 8	V1VolumeL		; sign (D7), value (D6..D0)
 0020	rw	 8	V2VolumeL
 0030	rw	 8	V3VolumeL
 0040	rw	 8	V4VolumeL
 0050	rw	 8	V5VolumeL
 0060	rw	 8	V6VolumeL
 0070	rw	 8	V7VolumeL

 0001	rw	 8	V0VolumeR		; volume for right
 0011	rw	 8	V1VolumeR		; sign (D7), value (D6..D0)
 0021	rw	 8	V2VolumeR
 0031	rw	 8	V3VolumeR
 0041	rw	 8	V4VolumeR
 0051	rw	 8	V5VolumeR
 0061	rw	 8	V6VolumeR
 0071	rw	 8	V7VolumeR

		14	V0Pitch			; pitch
		14	V1Pitch
		14	V2Pitch
		14	V3Pitch
		14	V4Pitch
		14	V5Pitch
		14	V6Pitch
		14	V7Pitch

 0002	rw	 8	V0PitchL		; pitch (bit 7..0)
 0012	rw	 8	V1PitchL
 0022	rw	 8	V2PitchL
 0032	rw	 8	V3PitchL
 0042	rw	 8	V4PitchL
 0052	rw	 8	V5PitchL
 0062	rw	 8	V6PitchL
 0072	rw	 8	V7PitchL

 0003	rw	 6	V0PitchH		; pitch (bit 13..8)
 0013	rw	 6	V1PitchH
 0023	rw	 6	V2PitchH
 0033	rw	 6	V3PitchH
 0043	rw	 6	V4PitchH
 0053	rw	 6	V5PitchH
 0063	rw	 6	V6PitchH
 0073	rw	 6	V7PitchH

 0004	rw	 8	V0SrcN			; source sample number
 0014	rw	 8	V1SrcN
 0024	rw	 8	V2SrcN
 0034	rw	 8	V3SrcN
 0044	rw	 8	V4SrcN
 0054	rw	 8	V5SrcN
 0064	rw	 8	V6SrcN
 0074	rw	 8	V7SrcN

 0005	rw	 8	V0ADSR1			; ADSR 1
 0015	rw	 8	V1ADSR1			; ADSR enabled (D7), DR (D6..D4), AR (D3..D0)
 0025	rw	 8	V2ADSR1
 0035	rw	 8	V3ADSR1
 0045	rw	 8	V4ADSR1
 0055	rw	 8	V5ADSR1
 0065	rw	 8	V6ADSR1
 0075	rw	 8	V7ADSR1

 0006	rw	 8	V0ADSR2			; ADSR 2
 0016	rw	 8	V1ADSR2			; SL (D7..D4), SR (D3..D0)
 0026	rw	 8	V2ADSR2
 0036	rw	 8	V3ADSR2
 0046	rw	 8	V4ADSR2
 0056	rw	 8	V5ADSR2
 0066	rw	 8	V6ADSR2
 0076	rw	 8	V7ADSR2

 0007	rw	 8	V0Gain			; GAIN setting
 0017	rw	 8	V1Gain			; Indirect (D7), Inc. (D6), Non-linear (D5), value (direct: D6..D0, else D4..D0)
 0027	rw	 8	V2Gain
 0037	rw	 8	V3Gain			; 0vvvvvvv  =  direct designation
 0047	rw	 8	V4Gain			; 110vvvvv  =  increase mode (linear)
 0057	rw	 8	V5Gain			; 111vvvvv  =  increase mode (bent line)
 0067	rw	 8	V6Gain			; 100vvvvv  =  decrease mode (linear)
 0077	rw	 8	V7Gain			; 101vvvvv  =  decrease mode (exponential)

 0008	r	 7	V0EnvX			; current value of the ADSR/Gain envelope constant (D6..D0)
 0018	r	 7	V1EnvX			; (content is set by DSP)
 0028	r	 7	V2EnvX
 0038	r	 7	V3EnvX
 0048	r	 7	V4EnvX
 0058	r	 7	V5EnvX
 0068	r	 7	V6EnvX
 0078	r	 7	V7EnvX

 0009	r	 8	V0OutX			; current value after envelope multiplication (current wave height value)
 0019	r	 8	V1OutX			; (content is set by DSP)
 0029	r	 8	V2OutX			; sign (D7), value (D6..D0)
 0039	r	 8	V3OutX
 0049	r	 8	V4OutX
 0059	r	 8	V5OutX
 0069	r	 8	V6OutX
 0079	r	 8	V7OutX



[ZST]
		 8	versn			; version #/100
		 8	curcyc			; cycles left in scanline
		16	curypos			; current y position
		 8	cacheud			; update cache every ? frames
		 8	ccud			; current cache increment
		 8	intrset			; interrupt set
		 8	cycpl			; cycles per scanline
		 8	cycphb			; cycles per hblank
		 8	spcon			; SPC Enable (1=enabled)
		16	stackand		; value to and stack to keep it from going to the wrong area
		16	stackor			; value to or stack to keep it from going to the wrong area

						; [65816 registers]
		16	xat
		 8	xdbt
		 8	xpbt
		16	xst
		16	xdt
		16	xxt
		16	xyt
		 8	xp
		 8	xe
		16	xpc
		 8	xirqb			; which bank the irqs start at
		 8	debugger		; Start with debugger (1=yes, 0=no)
		32	Curtableaddr		; Current table address
		 8	curnmi			; if in NMI (1) or not (0)
		32	cycpbl			; percentage left of CPU/SPC to run  (3.58 = 175)
		32	cycpblt			; percentage of CPU/SPC to run

						; [SNES PPU Registers]
		 8	sndrot			; rotates to use A,X or Y for sound skip
		 8	sndrot2			; rotates a random value for sound skip
		 8	INTEnab			; enables NMI (7) / VIRQ (5) / HIRQ (4) / JOY (0)
		 8	NMIEnab			; controlled in e65816 loop.  Sets to 81h
		16	VIRQLoc			; VIRQ Y location
		 8	vidbright		; screen brightness (0..15)
		 8	previdbr		; previous screen brightness
		 8	forceblnk		; force blanking on/off (80h=on)
		32	objptr			; pointer to object data in VRAM
		32	objptrn			; pointer2 to object data in VRAM
		 8	objsize1		; 1 = 8dot, 4=16 dot, 16=32 dot, 64=64 dot
		 8	objsize2		; large object size
		 8	objmovs1		; number of bytes to move/paragraph
		16	objadds1		; number of bytes to add/paragraph
		 8	objmovs2		; number of bytes to move/paragraph
		16	objadds2		; number of bytes to add/paragraph
		16	oamaddrt		; oam address
		16	oamaddrs		; oam address at beginning of vblank
		 8	objhipr			; highest priority object #
		 8	bgmode			; graphics mode (0..7)
		 8	bg3highst		; is 1 if background 3 has the highest priority
		 8	bgtilesz		; 0=8x8, 1=16x16; bit0=bg1, bit1=bg2, etc
		 8	mosaicon		; mosaic on, bit 0=bg1, bit1=bg2, etc
		 8	mosaicsz		; mosaic size in pixels
		16	bg1ptr			; pointer to background1
		16	bg2ptr			; pointer to background2
		16	bg3ptr			; pointer to background3
		16	bg4ptr			; pointer to background4
		16	bg1ptrb			; pointer to background1
		16	bg2ptrb			; pointer to background2
		16	bg3ptrb			; pointer to background3
		16	bg4ptrb			; pointer to background4
		16	bg1ptrc			; pointer to background1
		16	bg2ptrc			; pointer to background2
		16	bg3ptrc			; pointer to background3
		16	bg4ptrc			; pointer to background4
		16	bg1ptrd			; pointer to background1
		16	bg2ptrd			; pointer to background2
		16	bg3ptrd			; pointer to background3
		16	bg4ptrd			; pointer to background4
		 8	bg1scsize		; bg #1 screen size (0=1x1, 1=1x2, 2=2x1, 3=2x2)
		 8	bg2scsize		; bg #2 screen size (0=1x1, 1=1x2, 2=2x1, 3=2x2)
		 8	bg3scsize		; bg #3 screen size (0=1x1, 1=1x2, 2=2x1, 3=2x2)
		 8	bg4scsize		; bg #4 screen size (0=1x1, 1=1x2, 2=2x1, 3=2x2)
		16	bg1objptr		; pointer to tiles in background1
		16	bg2objptr		; pointer to tiles in background2
		16	bg3objptr		; pointer to tiles in background3
		16	bg4objptr		; pointer to tiles in background4
		16	bg1scrolx		; background 1 x position
		16	bg2scrolx		; background 2 x position
		16	bg3scrolx		; background 3 x position
		16	bg4scrolx		; background 4 x position
		16	bg1sx			; Temporary Variable for Debugging purposes
		16	bg1scroly		; background 1 y position
		16	bg2scroly		; background 2 y position
		16	bg3scroly		; background 3 y position
		16	bg4scroly		; background 4 y position
		16	addrincr		; vram increment (2, 64, 128, 256)
		 8	vramincr		; 0 = inrement at 2118/2139, 1 = 2119,213A
		 8	vramread		; 0 = address set, 1 = already read once
		32	vramaddr		; vram address
		16	cgaddr			; cg (palette) address
		 8	cgmod			; if cgram is modified or not
		16	scrnon			; main & sub screen on
		 8	scrndist		; which background is disabled
		16	resolutn		; screen resolution
		 8	multa			; multiplier A
		16	diva			; divisor C
		16	divres			; quotent of divc/divb
		16	multres			; result of multa * multb/remainder of divc/divb
		16	latchx			; latched x value
		16	latchy			; latched y value
		 8	latchxr			; low or high byte read for x value
		 8	latchyr			; low or high byte read for y value
		 8	frskipper		; used to control frame skipping
		 8	winl1			; window 1 left position
		 8	winr1			; window 1 right position
		 8	winl2			; window 2 left position
		 8	winr2			; window 2 right position
		 8	winbg1en		; Win1 on (IN/OUT) or Win2 on (IN/OUT) on BG1
		 8	winbg2en		; Win1 on (IN/OUT) or Win2 on (IN/OUT) on BG2
		 8	winbg3en		; Win1 on (IN/OUT) or Win2 on (IN/OUT) on BG3
		 8	winbg4en		; Win1 on (IN/OUT) or Win2 on (IN/OUT) on BG4
		 8	winobjen		; Win1 on (IN/OUT) or Win2 on (IN/OUT) on sprites
		 8	wincolen		; Win1 on (IN/OUT) or Win2 on (IN/OUT) on backarea
		 8	winlogica		; Window logic type for BG1 to 4
		 8	winlogicb		; Window logic type for Sprites and Backarea
		 8	winenabm		; Window logic enable for main screen
		 8	winenabs		; Window logic enable for sub screen
		 8	mode7set		; mode 7 settings
		16	mode7A			; A value for Mode 7
		16	mode7B			; B value for Mode 7
		16	mode7C			; C value for Mode 7
		16	mode7D			; D value for Mode 7
		16	mode7X0			; Center X for Mode 7
		16	mode7Y0			; Center Y for Mode 7
		 8	JoyAPos			; Old-Style Joystick Read Position for Joy 1 & 3
		 8	JoyBPos			; Old-Style Joystick Read Position for Joy 2 & 4
		32	compmult		; Complement Multiplication for Mode 7
		 8	joyalt			; temporary joystick alternation

		32	wramrwadr		; continuous read/write to wram address
		 8	irqon			; if IRQ has been called (80h) or not (0)
		 8	nexthdma		; HDMA data to execute once vblank ends
		 8	curhdma			; Currently executed hdma
		 8	hdmatype		; if first time executing hdma or not
		 5	coladdr			; red value of color to add
		 5	coladdg			; green value of color to add
		 5	coladdb			; blue value of color to add
		 8	colnull			; keep this 0 (when accessing colors by dword)
		 8	scaddset		; screen/fixed color addition settings
		 8	scaddtype		; which screen to add/sub
		 8	Voice0Disabl2		; Disable Voice 0
		 8	Voice1Disabl2		; Disable Voice 1
		 8	Voice2Disabl2		; Disable Voice 2
		 8	Voice3Disabl2		; Disable Voice 3
		 8	Voice4Disabl2		; Disable Voice 4
		 8	Voice5Disabl2		; Disable Voice 5
		 8	Voice6Disabl2		; Disable Voice 6
		 8	Voice7Disabl2		; Disable Voice 7

		 8	vraminctype

						; [New variables]
		 8	vramincby8on		; if increment by 8 is on
		 8	vramincby8left		; how many left
		 8	vramincby8totl		; how many in total (32, 64, 128)
		 8	vramincby8rowl		; how many left in that row (start at 8)
		16	vramincby8ptri		; increment by how many when rowl = 0

		 8	nexthprior
		 8	doirqnext

		16	vramincby8var
		 8	screstype
		 8	extlatch
		 8	cfield
		 8	interlval

		16	HIRQLoc			; HIRQ X location

		 8	KeyOnStA
		 8	KeyOnStB

		 8	SDD1BankA
		 8	SDD1BankB
		 8	SDD1BankC
		 8	SDD1BankD
		 8	vramread2		; previous character for vram read
		 8	nosprincr
		16	poamaddrs
		 8	ioportval
		 8	iohvlatch
		 8	ppustatus

						; ----------------------------------------------------------------

						; [SPC700 Status Area]

		32	spcPCRam		; Program Counter
		32	spcA			; The A register (general purpose)
		32	spcX			; The X register (general purpose)
		32	spcY			; The Y register (general purpose)
		32	spcP			; The processor status byte (Removed for each flags); NZ are not always processed...
		32	spcNZ			; The processor NZ flag (little speed up hack :) )

		32	spcS			; The stack pointer (always from 100 to 1FF) (added Ram)
		32	spcRamDP		; The direct page pointer
		32	spcCycle		; The Cycle Counter
		 8	reg1read		; read from 65816
		 8	reg2read		; read from 65816
		 8	reg3read		; read from 65816
		 8	reg4read		; read from 65816
		 8	timeron			; timer0 on
		 8	timincr0		; # of ticks before incrementing
		 8	timincr1		; # of ticks before incrementing
		 8	timincr2		; # of ticks before incrementing
		 8	timinl0			; ticks left before incrementing
		 8	timinl1			; ticks left before incrementing
		 8	timinl2			; ticks left before incrementing
		 8	timrcall		; alternating bit 0 to correctly timer timer1 & 2 to 8000hz

						; [DSP Status area]

		32	BRRPlace0		; Place in the BRRBuffer for Voice 0
		32	BRRTemp0		; Keep this 0
		32	BRRPlace1		; Place in the BRRBuffer for Voice 0
		32	BRRTemp1		; Keep this 0
		32	BRRPlace2		; Place in the BRRBuffer for Voice 0
		32	BRRTemp2		; Keep this 0
		32	BRRPlace3		; Place in the BRRBuffer for Voice 0
		32	BRRTemp3		; Keep this 0
		32	BRRPlace4		; Place in the BRRBuffer for Voice 0
		32	BRRTemp4		; Keep this 0
		32	BRRPlace5		; Place in the BRRBuffer for Voice 0
		32	BRRTemp5		; Keep this 0
		32	BRRPlace6		; Place in the BRRBuffer for Voice 0
		32	BRRTemp6		; Keep this 0
		32	BRRPlace7		; Place in the BRRBuffer for Voice 0
		32	BRRTemp7		; Keep this 0

		32	Voice0Freq		; Frequency of Voice 0 (Delta Freq)
		32	Voice1Freq		; Frequency of Voice 1 (Delta Freq)
		32	Voice2Freq		; Frequency of Voice 2 (Delta Freq)
		32	Voice3Freq		; Frequency of Voice 3 (Delta Freq)
		32	Voice4Freq		; Frequency of Voice 4 (Delta Freq)
		32	Voice5Freq		; Frequency of Voice 5 (Delta Freq)
		32	Voice6Freq		; Frequency of Voice 6 (Delta Freq)
		32	Voice7Freq		; Frequency of Voice 7 (Delta Freq)

		16	Voice0Pitch		; Previous Pitch for Voice 0
		16	Voice1Pitch		; Previous Pitch for Voice 1
		16	Voice2Pitch		; Previous Pitch for Voice 2
		16	Voice3Pitch		; Previous Pitch for Voice 3
		16	Voice4Pitch		; Previous Pitch for Voice 4
		16	Voice5Pitch		; Previous Pitch for Voice 5
		16	Voice6Pitch		; Previous Pitch for Voice 6
		16	Voice7Pitch		; Previous Pitch for Voice 7


		 8	Voice0Status		; 0=Not Playing 1=Playing
		 8	Voice1Status
		 8	Voice2Status
		 8	Voice3Status
		 8	Voice4Status
		 8	Voice5Status
		 8	Voice6Status
		 8	Voice7Status

		32	Voice0Ptr		; Ptr to Next BRR Block to be played
		32	Voice1Ptr
		32	Voice2Ptr
		32	Voice3Ptr
		32	Voice4Ptr
		32	Voice5Ptr
		32	Voice6Ptr
		32	Voice7Ptr
		32	Voice0LoopPtr		; Ptr to Loop BRR Block to be played
		32	Voice1LoopPtr		; Ptr to Loop BRR Block to be played
		32	Voice2LoopPtr		; Ptr to Loop BRR Block to be played
		32	Voice3LoopPtr		; Ptr to Loop BRR Block to be played
		32	Voice4LoopPtr		; Ptr to Loop BRR Block to be played
		32	Voice5LoopPtr		; Ptr to Loop BRR Block to be played
		32	Voice6LoopPtr		; Ptr to Loop BRR Block to be played
		32	Voice7LoopPtr		; Ptr to Loop BRR Block to be played

		32	Voice0BufPtr		; Ptr to Buffer Block to be played
		32	Voice1BufPtr		; Ptr to Buffer Block to be played
		32	Voice2BufPtr		; Ptr to Buffer Block to be played
		32	Voice3BufPtr		; Ptr to Buffer Block to be played
		32	Voice4BufPtr		; Ptr to Buffer Block to be played
		32	Voice5BufPtr		; Ptr to Buffer Block to be played
		32	Voice6BufPtr		; Ptr to Buffer Block to be played
		32	Voice7BufPtr		; Ptr to Buffer Block to be played

		32	SoundCounter		; Counter used for sound generation
		32	SoundCounter2		; Counter used for sound generation
		32	Voice0Prev0
		32	Voice1Prev0
		32	Voice2Prev0
		32	Voice3Prev0
		32	Voice4Prev0
		32	Voice5Prev0
		32	Voice6Prev0
		32	Voice7Prev0
		32	Voice0Prev1
		32	Voice1Prev1
		32	Voice2Prev1
		32	Voice3Prev1
		32	Voice4Prev1
		32	Voice5Prev1
		32	Voice6Prev1
		32	Voice7Prev1

		 8	Voice0Loop
		 8	Voice1Loop
		 8	Voice2Loop
		 8	Voice3Loop
		 8	Voice4Loop
		 8	Voice5Loop
		 8	Voice6Loop
		 8	Voice7Loop

		 8	Voice0End
		 8	Voice1End
		 8	Voice2End
		 8	Voice3End
		 8	Voice4End
		 8	Voice5End
		 8	Voice6End
		 8	Voice7End

		 8	Voice0Noise
		 8	Voice1Noise
		 8	Voice2Noise
		 8	Voice3Noise
		 8	Voice4Noise
		 8	Voice5Noise
		 8	Voice6Noise
		 8	Voice7Noise

		 8	Voice0Volume
		 8	Voice1Volume
		 8	Voice2Volume
		 8	Voice3Volume
		 8	Voice4Volume
		 8	Voice5Volume
		 8	Voice6Volume
		 8	Voice7Volume

		 8	Voice0VolumeR
		 8	Voice1VolumeR
		 8	Voice2VolumeR
		 8	Voice3VolumeR
		 8	Voice4VolumeR
		 8	Voice5VolumeR
		 8	Voice6VolumeR
		 8	Voice7VolumeR

		 8	Voice0VolumeL
		 8	Voice1VolumeL
		 8	Voice2VolumeL
		 8	Voice3VolumeL
		 8	Voice4VolumeL
		 8	Voice5VolumeL
		 8	Voice6VolumeL
		 8	Voice7VolumeL

		 8	Voice0Env
		 8	Voice1Env
		 8	Voice2Env
		 8	Voice3Env
		 8	Voice4Env
		 8	Voice5Env
		 8	Voice6Env
		 8	Voice7Env

		 8	Voice0Out
		 8	Voice1Out
		 8	Voice2Out
		 8	Voice3Out
		 8	Voice4Out
		 8	Voice5Out
		 8	Voice6Out
		 8	Voice7Out

						; 1 Attack, 2 Decrease,3 Sustain, 0 Gain
		 8	Voice0State
		 8	Voice1State
		 8	Voice2State
		 8	Voice3State
		 8	Voice4State
		 8	Voice5State
		 8	Voice6State
		 8	Voice7State

		32	Voice0Time
		32	Voice1Time
		32	Voice2Time
		32	Voice3Time
		32	Voice4Time
		32	Voice5Time
		32	Voice6Time
		32	Voice7Time

		32	Voice0Attack
		32	Voice1Attack
		32	Voice2Attack
		32	Voice3Attack
		32	Voice4Attack
		32	Voice5Attack
		32	Voice6Attack
		32	Voice7Attack

		32	Voice0Decay
		32	Voice1Decay
		32	Voice2Decay
		32	Voice3Decay
		32	Voice4Decay
		32	Voice5Decay
		32	Voice6Decay
		32	Voice7Decay

		 8	Voice0SustainL
		 8	Voice1SustainL
		 8	Voice2SustainL
		 8	Voice3SustainL
		 8	Voice4SustainL
		 8	Voice5SustainL
		 8	Voice6SustainL
		 8	Voice7SustainL

		 8	Voice0SustainL2
		 8	Voice1SustainL2
		 8	Voice2SustainL2
		 8	Voice3SustainL2
		 8	Voice4SustainL2
		 8	Voice5SustainL2
		 8	Voice6SustainL2
		 8	Voice7SustainL2

		32	Voice0SustainR
		32	Voice1SustainR
		32	Voice2SustainR
		32	Voice3SustainR
		32	Voice4SustainR
		32	Voice5SustainR
		32	Voice6SustainR
		32	Voice7SustainR

		32	Voice0SustainR2
		32	Voice1SustainR2
		32	Voice2SustainR2
		32	Voice3SustainR2
		32	Voice4SustainR2
		32	Voice5SustainR2
		32	Voice6SustainR2
		32	Voice7SustainR2

		32	Voice0IncNumber
		32	Voice1IncNumber
		32	Voice2IncNumber
		32	Voice3IncNumber
		32	Voice4IncNumber
		32	Voice5IncNumber
		32	Voice6IncNumber
		32	Voice7IncNumber

		32	Voice0SLenNumber
		32	Voice1SLenNumber
		32	Voice2SLenNumber
		32	Voice3SLenNumber
		32	Voice4SLenNumber
		32	Voice5SLenNumber
		32	Voice6SLenNumber
		32	Voice7SLenNumber

		32	Voice0SEndNumber
		32	Voice1SEndNumber
		32	Voice2SEndNumber
		32	Voice3SEndNumber
		32	Voice4SEndNumber
		32	Voice5SEndNumber
		32	Voice6SEndNumber
		32	Voice7SEndNumber

		32	Voice0SEndLNumber
		32	Voice1SEndLNumber
		32	Voice2SEndLNumber
		32	Voice3SEndLNumber
		32	Voice4SEndLNumber
		32	Voice5SEndLNumber
		32	Voice6SEndLNumber
		32	Voice7SEndLNumber

		32	Voice0DecreaseNumber
		32	Voice1DecreaseNumber
		32	Voice2DecreaseNumber
		32	Voice3DecreaseNumber
		32	Voice4DecreaseNumber
		32	Voice5DecreaseNumber
		32	Voice6DecreaseNumber
		32	Voice7DecreaseNumber

		32	Voice0EnvInc
		32	Voice1EnvInc
		32	Voice2EnvInc
		32	Voice3EnvInc
		32	Voice4EnvInc
		32	Voice5EnvInc
		32	Voice6EnvInc
		32	Voice7EnvInc

						; 0 = Direct, 1 = Increase, 2 = Increase2, 3 = Decrease, 4 = Decrease2
		 8	Voice0GainType
		 8	Voice1GainType
		 8	Voice2GainType
		 8	Voice3GainType
		 8	Voice4GainType
		 8	Voice5GainType
		 8	Voice6GainType
		 8	Voice7GainType

		32	Voice0GainTime
		32	Voice1GainTime
		32	Voice2GainTime
		32	Voice3GainTime
		32	Voice4GainTime
		32	Voice5GainTime
		32	Voice6GainTime
		32	Voice7GainTime

		 8	Voice0Starting
		 8	Voice1Starting
		 8	Voice2Starting
		 8	Voice3Starting
		 8	Voice4Starting
		 8	Voice5Starting
		 8	Voice6Starting
		 8	Voice7Starting

		32	Freqdisp
		32	SBRateb

		 8	Voice0Looped
		 8	Voice1Looped
		 8	Voice2Looped
		 8	Voice3Looped
		 8	Voice4Looped
		 8	Voice5Looped
		 8	Voice6Looped
		 8	Voice7Looped



[HexViewer arrays]
 APU			DSP RAM			; 256
 APU			SPC RAM			; 65536
 cart			ROM			; [cart]
 cart			SRAM			; [cart]
 SNES			CGRAM			; 256 * 2
 SNES			OAM			; (128 * 4) + (128 * 2/8)
 SNES			VRAM			; 65536
 SNES			WRAM			; 65536 * 2
 ZST			BRRBuffer		; 32
 ZST			dmadata			; 129
 ZST			extra chip info		; [cart]
 ZST			FutureExpand		; 244
 ZST			FutureExpandS		; 192
 ZST			hdmadata		; 152
 ZST			pcgram			; 256 * 2
 ZST			preview			; 64 * 56 * 2
 ZST			spcRom			; 80
 ZST			tempdat			; 477
 ZST			zsmesg			; 26 + 1


[SceneViewer info rows]
{screen}
base height = 239
BG mode
BG3 (priority 1) on top
brightness
color window
counter (H/V)
EXTBG
field (0..1)
fixed color
forced blanking
H-512 mode
interlace
internal screen size
mask window 1 xpos.
mask window 2 xpos.
mosaic size
PAL mode
range over
time over

{OBJ}
enabled on main
enabled on sub
highest priority sprite
single lines in interlace
tile base 1
tile base 2
tile size 1 (small)
tile size 2 (big)

{backgrounds}
bits per pixel
enabled: main
enabled: sub
mosaic
offset (x, y)
size
tile base
tile size
tilemap base
tilemap size

{mask window 1 / 2}
enabled
inversed
on main
on sub
1-2 logic

{Mode7}
A
B
C
D
bits per pixel
center
flip
offset
screen over data

{color math}
BG1
BG2
BG3
BG4
OBJ
BACK
direct color mode
half result mode
operation
operator

