3/4KY OverviewoftheHardware
3/4C EOVERVIEW OF THE HARDWARE                                MacintoshHardware
_______________________________________________________________________________

The Macintosh and Macintosh Plus computers contain a Motorola MC68000 microprocessor
clocked at 7.8336 megahertz, random access memory (RAM), read-only memory (ROM), and
several chips that enable them to communicate with external devices. There are five
I/O devices:EEthe video display; the sound generator; a Synertek SY6522 Versatile
Interface Adapter (VIA) for the mouse and keyboard; a Zilog Z8530 Serial Communications
Controller (SCC) for serial communication; and an Apple custom chip, called the IWM
(OIntegrated Woz MachineO) for disk control.

In addition to the five I/O devices found in the Macintosh 128K, 512K, and 512K
enhanced (the video display, sound generator, VIA, SCC and IWM), the Macintosh Plus
contains a NCR 5380 Small Computer Standard Interface (SCSI) chip for high-speed
parallel communication with devices such as hard disks.

Features of the Macintosh 512K enhanced (not found in the Macintosh 128K and 512K)
are:

    800K internal disk drive
    128K ROM

Features of the Macintosh Plus are:

    800K internal disk drive
    128K ROM
    SCSI high-speed peripheral port
    1Mb RAM, expandable to 2Mb, 2.5Mb, or 4Mb.
    2 Mini-8 connectors for serial ports, replacing the 2 DB-9 connectors
     found on the Macintosh 128K, 512K, and 512K enhanced.
    keyboard with built-in cursor keys and numeric keypad

The Macintosh uses memory-mapped I/O, which means that each device in the system is
accessed by reading or writing to specific locations in the address space of the
computer. Each device contains logic that recognizes when itOs being accessed and
responds in the appropriate manner.

The MC68000 can directly access 16 megabytes (Mb) of address space. In the Macintosh,
this is divided into four equal sections. The first four Mb are for RAM, the second
four Mb are for ROM, the third are for the SCC, and the last four are for the IWM and
the VIA. Since each of the devices within the blocks has far fewer than four Mb of
individually addressable locations or registers, the addresses within each block
Owrap aroundO and are repeated several times within the block.

In the Macintosh Plus, the 16 Mb of addressable space is also divided into four equal
sections. The first four megabytes are for RAM, the second four megabytes are for ROM
and SCSI, the third are for the SCC, and the last four are for the IWM and the VIA.
Since the devices within each block may have far fewer than four megabytes of individually
addressable locations or registers, the addressing for a device may Owrap aroundO (a
particular register appears at several different addresses) within its block.

_______________________________________________________________________________

ERAM

RAM is the Oworking memoryO of the system. Its base address is address 0. The first
256 bytes of RAM (addresses 0 through $FF) are used by the MC68000 as exception
vectors; these are the addresses of the routines that gain control whenever an exception
such as an interrupt or a trap occurs. (The summary at the end of this chapter includes
a list of all the exception vectors.) RAM also contains the system and application
heaps, the stack, and other information used by applications. In addition, the following
hardware devices share the use of RAM with the MC68000:

    the video display, which reads the information for the display from
     one of two screen buffers
    the sound generator, which reads its information from one of two
     sound buffers
    the disk speed controller, which shares its data space with the
     sound buffers

The MC68000 accesses to RAM are interleaved (alternated) with the video
displayOs accesses during the active portion of a screen scan line (video scanning is
described in the next section). The sound generator and disk speed controller are
given the first access after each scan line. At all other times, the MC68000 has
uninterrupted access to RAM, increasing the average RAM access rate to about 6 megahertz
(MHz).

The Macintosh Plus RAM is provided in four packages known as Single In-line Memory
Modules (SIMMs). Each SIMM contains eight surface-mounted Dynamic RAM
(DRAM) chips on a small printed circuit board with electrical OfingerO contacts along
one edge. Various RAM configurations are possible depending on whether two or four
SIMMs are used and on the density of the DRAM chips that are plugged into the SIMMs:

    If the SIMMs contain 256K-bit DRAM chips, two SIMMs will provide 512K
     bytes of RAM, or four SIMMs will provide 1Mb of RAM (this is the standard
     configuration).
    If the SIMMs contain 1M-bit DRAM chips, two SIMMs will provide 2Mb of
     RAM, or four SIMMs will provide 4Mb of RAM.
    If two of the SIMMs contain 1M-bit DRAM chips, and two of the SIMMs
     contain 256K-bit DRAM chips, then these four SIMMs will provide 2.5Mb
     of RAM. For this configuration, the 1M-bit SIMMs must be placed in the
     sockets closest to the 68000 CPU.

Warning:  Other configurations, such as a single SIMM or a pair of SIMMs
          containing DRAMs of different density, are not allowed. If only
          two SIMMs are installed, they must be placed in the sockets closest
          to the MC68000.

The SIMMs can be changed by simply releasing one and snapping in another. However,
there are also two resistors on the Macintosh Plus logic board (in the area labelled
ORAM SIZEO) which tell the electronics how much RAM is installed. If two SIMMs are
plugged in, resistor R9 (labeled OONE ROWO) must be installed; if four SIMMs are
plugged in, this resistor must be removed. Resistor R8
(labelled O256K BITO) must be installed if all of the SIMMs contain 256K-bit DRAM
chips. If either two or four of the SIMMs contain 1M-bit chips, resistor R8 must be
removed.

Each time you turn on the Macintosh Plus, system software does a memory test and
determines how much RAM is present in the machine. This information is stored in the
global variable MemTop, which contains the address (plus one) of the last byte in
RAM.

_______________________________________________________________________________

EROM

ROM is the systemOs permanent read-only memory. Its base address, $400000, is available
as the constant romStart and is also stored in the global variable ROMBase. ROM
contains the routines for the Toolbox and Operating System, and the various system
traps. Since the ROM is used exclusively by the MC68000,
itOs always accessed at the full processor rate of 7.83 MHz.

The address space reserved for the device I/O contains blocks devoted to each of the
devices within the computer. This region begins at address $800000 and continues to
the highest address at $FFFFFF.

Note:EESince the VIA is involved in some way in almost every operation of the
       Macintosh, the following sections frequently refer to the VIA and
       VIA-related constants. The VIA itself is described later, and all the
       constants are listed in the summary at the end of this chapter.

The Macintosh Plus contains two 512K-bit (64K x 8) ROM chips, providing 128K bytes of
ROM. This is the largest size of ROM that can be installed in a Macintosh 128K, 512K,
or 512K enhanced. The Macintosh Plus ROM sockets, however, can accept ROM chips of up
to 1M-bit (128K x 8) in size. A configuration of two 1M-bit ROM chips would provide
256K bytes of ROM.

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3/4KY TheVideoInterface
3/4C ETHE VIDEO INTERFACE                                     MacintoshHardware
_______________________________________________________________________________

The video display is created by a moving electron beam that scans across the screen,
turning on and off as it scans in order to create black and white pixels. Each pixel
is a square, approximately 1/74 inch on a side.

To create a screen image, the electron beam starts at the top left corner of the
screen (see Figure 1). The beam scans horizontally across the screen from left to
right, creating the top line of graphics. When it reaches the last pixel on the right
end of the top line it turns off, and continues past the last pixel to the physical
right edge of the screen. Then it flicks invisibly back to the left edge and moves
down one scan line. After tracing across the black border, it begins displaying the
data in the second scan line. The time between the display of the rightmost pixel on
one line and the leftmost pixel on the next is called the horizontal blanking interval.
When the electron beam reaches the last pixel of the last (342nd) line on the screen,
it traces out to the right edge and then flicks up to the top left corner, where it
traces the left border and then begins once again to display the top line. The time
between the last pixel on the bottom line and the first one on the top line is called
the vertical blanking interval. At the beginning of the vertical blanking interval,
the VIA generates a vertical blanking interrupt.

The pixel clock rate (the frequency at which pixels are displayed) is 15.6672 MHz, or
about .064 microseconds (usec) per pixel. For each scan line, 512 pixels are drawn on
the screen, requiring 32.68 usec. The horizontal blanking interval takes the time of
an additional 192 pixels, or 12.25 usec. Thus, each full scan line takes 44.93 usec,
which means the horizontal scan rate is 22.25 kilohertz.

Refer to Figure 1.

Figure 1DVideo Scanning Pattern

A full screen display consists of 342 horizontal scan lines, occupying 15367.65 usec,
or about 15.37 milliseconds (msec). The vertical blanking interval takes the time of
an additional 28 scan lines1258.17 usec, or about 1.26 msec. This means the full
screen is redisplayed once every 16625.8 usec. ThatOs about 16.6 msec per frame,
which means the vertical scan rate (the full screen display frequency) is 60.15
hertz.

The video generator uses 21,888 bytes of RAM to compose a bit-mapped video image 512
pixels wide by 342 pixels tall. Each bit in this range controls a single pixel in the
image:EEA 0 bit is white, and a 1 bit is black.

There are two screen buffers (areas of memory from which the video circuitry can read
information to create a screen display):EEthe main buffer and the alternate buffer.
The starting addresses of the screen buffers depend on how much memory you have in
your Macintosh. In a Macintosh 128K, the main screen buffer starts at $1A700 and the
alternate buffer starts at $12700; for a 512K Macintosh, add $60000 to these numbers.

Warning:  To be sure you donOt use the wrong area of memory and to maintain
          compatibility with future Macintosh systems, you should get the
          video base address and bit map dimensions from screenBits (see
          the QuickDraw chapter).

Each scan line of the screen displays the contents of 32 consecutive words of memory,
each word controlling 16 horizontally adjacent pixels. In each word, the high-order
bit (bit 15) controls the leftmost pixel and the low-order bit
(bit 0) controls the rightmost pixel. The first word in each scan line follows the
last word on the line above it. The starting address of the screen is thus in the top
left corner, and the addresses progress from there to the right and down, to the last
byte in the extreme bottom right corner.

Normally, the video display doesnOt flicker when you read from or write to it, because
the video memory accesses are interleaved with the processor accesses. But if youOre
creating an animated image by repeatedly drawing the graphics in quick succession, it
may appear to flicker if the electron beam displays it when your program hasnOt
finished updating it, showing some of the new image and some of the old in the same
frame.

One way to prevent flickering when youOre updating the screen continuously is to use
the vertical and horizontal blanking signals to synchronize your updates to the
scanning of video memory. Small changes to your screen can be completed entirely
during the interval between frames (the first 1.26 msec following a vertical blanking
interrupt), when nothing is being displayed on the screen. When making larger changes,
the trick is to keep your changes happening always ahead of the spot being displayed
by the electron beam, as it scans byte by byte through the video memory. Changes you
make in the memory already passed over by the scan spot wonOt appear until the next
frame. If you start changing your image when the vertical blanking interrupt occurs,
you have 1.26 msec of unrestricted access to the image. After that, you can change
progressively less and less of your image as itOs scanned onto the screen, starting
from the top
(the lowest video memory address). From vertical blanking interrupt, you have only
1.26 msec in which to change the first (lowest address) screen location, but you have
almost 16.6 msec to change the last (highest address) screen location.

Another way to create smooth, flicker-free graphics, especially useful with changes
that may take more 16.6 msec, is to use the two screen buffers as alternate displays.
If you draw into the one thatOs currently not being displayed, and then switch the
buffers during the next vertical blanking, your graphics will change all at once,
producing a clean animation. (See the Vertical Retrace Manager chapter to find out
how to specify tasks to be performed during vertical blanking.)

If you want to use the alternate screen buffer, youOll have to specify this to the
Segment Loader (see the Segment Loader chapter for details). To switch to the alternate
screen buffer, clear the following bit of VIA data register A
(vBase+vBufA):

  vPage2    .EQU    6    ;0 = alternate screen buffer

For example:

  BCLR    #vPage2,vBase+vBufA

To switch back to the main buffer, set the same bit.

Warning:  Whenever you change a bit in a VIA data register, be sure to
          leave the other bits in the register unchanged.

Warning:  The alternate screen buffer may not be supported in future
          versions of the Macintosh.

The starting addresses of the Macintosh Plus screen buffers depend on the amount of
memory present in the machine. The following table shows the starting address of the
main and the alternate screen buffer for various memory configurations of the Macintosh
Plus:

  System                   Main Screen    Alternate

  Macintosh Plus, 1Mb      $FA700         $F2700
  Macintosh Plus, 2Mb      $1FA700        $1F2700
  Macintosh Plus, 2.5Mb    $27A700        $272700
  Macintosh Plus, 4Mb      $3FA700        $3F2700

Warning:  To ensure that software will run on Macintoshes of different memory
          size, as well as on future Macintoshes, use the address stored in
          the global variable ScrnBase. Also, the alternate screen buffer may
          not be available in future versions of the Macintosh and may not be
          found in some software configurations of current Macintoshes.

_______________________________________________________________________________


3/4KY TheSoundGenerator
3/4C ETHE SOUND GENERATOR                                     MacintoshHardware
_______________________________________________________________________________

The Macintosh sound circuitry uses a series of values taken from an area of RAM to
create a changing waveform in the output signal. This signal drives a small speaker
inside the Macintosh and is connected to the external sound jack on the back of the
computer. If a plug is inserted into the external sound jack, the internal speaker is
disabled. The external sound line can drive a load of 600 or more ohms, such as the
input of almost any audio amplifier, but not a directly connected external speaker.

The sound generator may be turned on or off by writing 1 (off) or 0 (on) to the
following bit of VIA data register B (vBase+vBufB):

  vSndEnb    .EQU    7    ;0 = sound enabled, 1 = disabled

For example:

  BSET    #vSndEnb,vBase+vBufB    ;turn off sound

By storing a range of values in the sound buffer, you can create the corresponding
waveform in the sound channel. The sound generator uses a form of pulse-width encoding
to create sounds. The sound circuitry reads one word in the sound buffer during each
horizontal blanking interval (including the
OvirtualO intervals during vertical blanking) and uses the high-order byte of the
word to generate a pulse of electricity whose duration (width) is proportional to the
value in the byte. Another circuit converts this pulse into a voltage thatOs attenuated
(reduced) by a three-bit value from the VIA. This reduction corresponds to the current
setting of the volume level. To set the volume directly, store a three-bit number in
the low-order bits of VIA data register A (vBase+vBufA). You can use the following
constant to isolate the bits involved:

  vSound    .EQU    7    ;sound volume bits

HereOs an example of how to set the sound level:

  MOVE.B    vBase+vBufA,D0    ;get current value of register A
  ANDI.B    #255-vSound,D0    ;clear the sound bits
  ORI.B     #3,D0             ;set medium sound level
  MOVE.B    D0,vBase+vBufA    ;put the data back

After attenuation, the sound signal is passed to the audio output line.
The sound circuitry scans the sound buffer at a fixed rate of 370 words per video
frame, repeating the full cycle 60.15 times per second. To create sounds with frequencies
other than multiples of the basic scan rate, you must store phase-shifted patterns
into the sound buffer between each scan. You can use the vertical and horizontal
blanking signals (available in the VIA) to synchronize your sound buffer updates to
the buffer scan. You may find that itOs much easier to use the routines in the Sound
Driver to do these functions.

Warning:  The low-order byte of each word in the sound buffer is used to
          control the speed of the motor in the disk drive. DonOt store
          any information there, or youOll interfere with the disk I/O.

There are two sound buffers, just as there are two screen buffers. The address of the
main sound buffer is stored in the global variable SoundBase and is also available as
the constant soundLow. The main sound buffer is at $1FD00 in a 128K Macintosh, and
the alternate buffer is at $1A100; for a 512K Macintosh, add $60000 to these values.
Each sound buffer contains 370 words of data. As when you want to use the alternate
screen buffer, youOll have to specify to the Segment Loader that you want the alternate
buffer (see the Segment Loader chapter for details). To select the alternate sound
buffer for output, clear the following bit of VIA data register A (vBase+vBufA):

  vSndPg2    .EQU    3    ;0 = alternate sound buffer

To return to the main buffer, set the same bit.

Warning:  Be sure to switch back to the main sound buffer before doing a
          disk access, or the disk wonOt work properly.

Warning:  The alternate sound buffer may not be supported in future
          versions of the Macintosh.

ThereOs another way to generate a simple, square-wave tone of any frequency, using
almost no processor intervention. To do this, first load a constant value into all
370 sound buffer locations (use $00Os for minumum volume, $FFOs for maximum volume).
Next, load a value into the VIAOs timer 1 latches, and set the high-order two bits of
the VIAOs auxiliary control register (vBase+vACR) for
Osquare wave outputO from timer 1. The timer will then count down from the latched
value at 1.2766 usec/count, over and over, inverting the vSndEnb bit of VIA register
B (vBase+vBufB) after each count down. This takes the constant voltage being generated
from the sound buffer and turns it on and off, creating a square-wave sound whose
period is

  2 * 1.2766 usec * timer 1Os latched value

Note:EEYou may want to disable timer 1 interrupts during this process (bit 6
       in the VIAOs interrupt enable register, which is at vBase+vIER).

To stop the square-wave sound, reset the high-order two bits of the auxiliary control
register.

Note:EESee the SY6522 technical specifications for details of the VIA
       registers. See also OSound Driver HardwareO in the Sound Driver
       chapter.

Figure 2 shows a block diagram for the sound port.

The starting addresses of the Macintosh Plus sound buffers depend on the amount of
memory present in the machine. The following table shows the starting address of the
main and the alternate sound buffer for various memory configurations of the Macintosh
Plus:

  System                   Main Sound    Alternate
  Macintosh Plus, 1Mb      $FFD00        $FA100
  Macintosh Plus, 2Mb      $1FFD00       $1FA100
  Macintosh Plus, 2.5Mb    $27FD00       $27A100
  Macintosh Plus, 4Mb      $3FFD00       $3FA100

Warning:  To ensure that software will run on Macintoshes of different memory
          size, as well as future Macintoshes, use the address stored in the
          global variable SoundBase. Also, the alternate sound buffer may not
          be available in future versions of the Macintosh and may not be found
          in some software configurations of current Macintoshes.

_______________________________________________________________________________


3/4KY TheSCC
3/4C ETHE SCC                                                 MacintoshHardware
_______________________________________________________________________________

The two serial ports are controlled by a Zilog Z8530 Serial Communications Controller
(SCC). The port known as SCC port A is the one with the modem icon on the back of the
Macintosh. SCC port B is the one with the printer icon.

Macintosh serial ports conform to the EIA standard RS422, which differs from the more
common RS232C standard. While RS232C modulates a signal with respect to a common
ground (Osingle-endedO transmission), RS422 modulates two signals against each other
(OdifferentialO transmission). The RS232C receiver senses whether the received signal
is sufficiently negative with respect to ground to be a logic O1O, whereas the RS422
receiver simply senses which line is more negative than the other. This makes RS422
more immune to noise and interference, and more versatile over longer distances. If
you ground the positive side of each RS422 receiver and leave unconnected the positive
side of each transmitter, youOve converted to EIA standard RS423, which can be used
to communicate with most RS232C devices over distances up to fifty feet or so.

Refer to Figure 2.

Figure 2DDiagram of Sound Port

The serial inputs and outputs of the SCC are connected to the ports through differential
line drivers (26LS30) and receivers (26LS32). The line drivers can be put in the
high-impedance mode between transmissions, to allow other devices to transmit over
those lines. A driver is activated by lowering the SCCOs Request To Send (RTS) output
for that port. Port A and port B are identical except that port A (the modem port)
has a higher interrupt priority, making it more suitable for high-speed communication.

Figure 3 shows the DB-9 pinout for the SCC output jacks.

Refer to Figure 3.

Figure 3DPinout for SCC Output Jacks

Warning:  Do not draw more than 100 milliamps at +12 volts, and
          200 milliamps at +5 volts from all connectors combined.

Each portOs input-only handshake line (pin 7) is connected to the SCCOs Clear To Send
(CTS) input for that port, and is designed to accept an external
deviceOs Data Terminal Ready (DTR) handshake signal. This line is also connected to
the SCCOs external synchronous clock (TRxC) input for that port, so that an external
device can perform high-speed synchronous data exchange. Note that you canOt use the
line for receiving DTR if youOre using it to receive a high-speed data clock.

The handshake line is sensed by the Macintosh using the positive (noninverting) input
of one of the standard RS422 receivers (26LS32 chip), with the negative input grounded.
The positive input was chosen because this configuration is more immune to noise when
no active device is connected to pin 7.

Note:EEBecause this is a differential receiver, any handshake or clock signal
       driving it must be Obi-polarO, alternating between a positive voltage
       and a negative voltage, with respect to the internally grounded negative
       input. If a device tries to use ground (0 volts) as one of its handshake
       logic levels, the Macintosh will receive that level as an indeterminate
       state, with unpredicatbale results.

The SCC itself (at its PCLK pin) is clocked at 3.672 megahertz. The internal synchronous
clock (RTxC) pins for both ports are also connected to this 3.672 MHz clock. This is
the clock that, after dividing by 16, is normally fed to the SCCOs internal baud-rate
generator.

The SCC chip generates level-2 processor interrupts during I/O over the serial lines.
For more information about SCC interrupts, see the Device Manager chapter.

The locations of the SCC control and data lines are given in the following table as
offsets from the constant sccWBase for writes, or sccRBase for reads. These base
addresses are also available in the global variables SCCWr and SCCRd. The SCC is on
the upper byte of the data bus, so you must use only even-addressed byte reads (a
byte read of an odd SCC read address tries to reset the entire SCC). When writing,
however, you must use only odd-addressed byte writes (the MC68000 puts your data on
both bytes of the bus, so it works correctly). A word access to any SCC address will
shift the phase of the computerOs high-frequency timing by 128 nanoseconds (system
software adjusts it correctly during the system startup process).

  Location          Contents

  sccWBase+aData    Write data register A
  sccRBase+aData    Read data register A
  sccWBase+bData    Write data register B
  sccRBase+bData    Read data register B
  sccWBase+aCtl     Write control register A
  sccRBase+aCtl     Read control register A
  sccWBase+bCtl     Write control register B
  sccRBase+bCtl     Read control register B

Warning:  DonOt access the SCC chip more often than once every 2.2 usec. The
          SCC requires that much time to let its internal lines stabilize.

Refer to the technical specifications of the Zilog Z8530 for the detailed bit maps
and control methods (baud rates, protocols, and so on) of the SCC.

Figure 4 shows a circuit diagram for the serial ports.

Refer to Figure 4.

Figure 4DDiagram of Serial Ports

The Macintosh Plus uses two Mini-8 connectors for the two serial ports, replacing the
two DB-9 connectors used for the serial ports on the Macintosh 128K, 512K, and 512K
enhanced.

The Mini-8 connectors provide an output handshake signal, but do not provide the +5
volts and +12 volts found on the Macintosh 128K, 512K, and 512K enhanced serial
ports.

The output handshake signal for each Macintosh Plus serial port originates at the
SCCOs Data Terminal Ready (DTR) output for that port, and is driven by an RS423 line
driver. Other signals provided include input handshake/external clock, Transmit Data
+ and D, and Receive Data + and D.

Figure 5 shows the Mini-8 pinout for the SCC serial connectors.

Refer to Figure 5.

Figure 5DPinout for SCC Serial Connectors

Figure 6 shows a circuit diagram for the Macintosh Plus serial ports.

Refer to Figure 6.

Figure 6DCircuit Diagram for the Macintosh Plus Serial Ports

_______________________________________________________________________________


3/4KY The.Mouse
3/4C ETHE MOUSE                                               MacintoshHardware
_______________________________________________________________________________

The DB-9 connector labeled with the mouse icon connects to the Apple mouse
(Apple II, AppleEIII, Lisa, and Macintosh mice are electrically identical). The mouse
generates four square-wave signals that describe the amount and direction of the
mouseOs travel. Interrupt-driven routines in the Macintosh ROM convert this information
into the corresponding motion of the pointer on the screen. By turning an option
called mouse scaling on or off in the Control Panel desk accessory, the user can
change the amount of screen pointer motion that corresponds to a given mouse motion,
depending on how fast the mouse is moved; for more information about mouse scaling,
see the discussion of parameter RAM in the Operating System Utilities chapter.

Note:EEThe mouse is a relative-motion device; that is, it doesnOt report
       where it is, only how far and in which direction itOs moving. So if
       you want to connect graphics tablets, touch screens, light pens, or
       other absolute-position devices to the mouse port, you must either
       convert their coordinates into motion information or install your
       own device-handling routines.

The mouse operates by sending square-wave trains of information to the Macintosh that
change as the velocity and direction of motion change. The rubber-coated steel ball
in the mouse contacts two capstans, each connected to an interrupter wheel:EEMotion
along the mouseOs X axis rotates one of the wheels and motion along the Y axis rotates
the other wheel.

The Macintosh uses a scheme known as quadrature to detect which direction the mouse
is moving along each axis. ThereOs a row of slots on an interrupter wheel, and two
beams of infrared light shine through the slots, each one aimed at a phototransistor
detector. The detectors are offset just enough so that, as the wheel turns, they
produce two square-wave signals (called the interrupt signal and the quadrature
signal) 90 degrees out of phase. The quadrature signal precedes the interrupt signal
by 90 degrees when the wheel turns one way, and trails it when the wheel turns the
other way.

The interrupt signals, X1 and Y1, are connected to the SCCOs DCDA and DCDB inputs,
respectively, while the quadrature signals, X2 and Y2, go to inputs of the VIAOs data
register B. When the Macintosh is interrupted (from the SCC) by the rising edge of a
mouse interrupt signal, it checks the VIA for the state of the quadrature signal for
that axis:EEIf itOs low, the mouse is moving to the left (or down), and if itOs high,
the mouse is moving to the right (or up). When the SCC interrupts on the falling
edge, a high quadrature level indicates motion to the left (or down) and a low quadrature
level indicates motion to the right (or up):

  SCC                VIA                 Mouse

  Mouse interrupt    Mouse quadrature    Motion direction in
  X1 (or Y1)         X2 (or Y2)          X (or Y) axis
  Positive edge      Low                 Left (or down)
                     High                Right (or up)
  Negative edge      Low                 Right (or up)
                     High                Left (or down)

Figure 7 shows the interrupt (Y1) and quadrature (Y2) signals when the mouse is moved
downwards.

The switch on the mouse is a pushbutton that grounds pin 7 on the mouse connector
when pressed. The state of the button is checked by software during each vertical
blanking interrupt. The small delay between each check is sufficient to debounce the
button. You can look directly at the mouse buttonOs state by examining the following
bit of VIA data register B (vBase+vBufB):

  vSW    .EQU    3    ;0 = mouse button is down

If the bit is clear, the mouse button is down. However, itOs recommended that you let
the Operating System handle this for you through the event mechanism.

Figure 8 shows the DB-9 pinout for the mouse jack at the back of the Macintosh.

Refer to Figure 7.

Figure 7DMouse Mechanism

Refer to Figure 8.

Figure 8DPinout for Mouse Jack

Warning:  Do not draw more than 200 milliamps at +5 volts from all
          connectors combined.

Figure 9 shows a circuit diagram for the mouse port.

Refer to Figure 9.

Figure 9DDiagram of Mouse Port

_______________________________________________________________________________


3/4KY TheKeyboardandKeypad
3/4C ETHE KEYBOARD AND KEYPAD                                 MacintoshHardware
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The Macintosh keyboard and numeric keypad each contain an Intel 8021 microprocessor
that scans the keys. The 8021 contains ROM and RAM, and is programmed to conform to
the interface protocol described below.

The keyboard plugs into the Macintosh through a four-wire RJ-11 telephone-style jack.
If a numeric keypad is installed in the system, the keyboard plugs into it and it in
turn plugs into the Macintosh. Figure 10 shows the pinout for the keyboard jack on
the Macintosh, on the keyboard itself, and on the numeric keypad.

Refer to Figure 10.

Figure 10DPinout for Keyboard Jack

Warning:  Do not draw more than 200 milliamps at +5 volts from all
          connectors combined.

The Macintosh Plus keyboard, which includes a built-in numeric keypad, contains a
microprocessor that scans the keys. The microprocessor contains ROM and RAM, and is
programmed to conform to the same keyboard interface protocol described below.

The Macintosh Plus keyboard reproduces all of the key-down transitions produced by
the keyboard and optional keypad used by the Macintosh 128K, 512K, and 512K enhanced;
the Macintosh Plus keyboard is also completely compatible with these other machines.
If a key transition occurs for a key that used to be on the optional keypad in lowercase,
the Macintosh Plus keyboard still responds to an Inquiry command by sending back the
Keypad response ($79) to the Macintosh Plus. If a key transition occurs for an key
that used to be on the optional keypad in uppercase, the Macintosh Plus keyboard
responds to an Inquiry command by sending back the Shift KeyDdown Transition response
($71), followed by the Keypad response ($79). The responses for key-down transitions
on the original Macintosh and Macintosh Plus are shown (in hexadecimal) in Figure
11.

Refer to Figure 11.

Figure 11DKey-Down Transitions

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EKeyboard Communication Protocol

The keyboard data line is bidirectional and is driven by whatever device is sending
data. The keyboard clock line is driven by the keyboard only. All data transfers are
synchronous with the keyboard clock. Each transmission consists of eight bits, with
the highest-order bits first.

When sending data to the Macintosh, the keyboard clock transmits eight 330-usec
cycles (160 usec low, 170 usec high) on the normally high clock line. It places the
data bit on the data line 40 usec before the falling edge of the clock line and
maintains it for 330 usec. The data bit is clocked into the MacintoshOs VIA shift
register on the rising edge of the keyboard clock cycle.

When the Macintosh sends data to the keyboard, the keyboard clock transmits eight
400-usec cycles (180 usec low, 220 usec high) on the clock line. On the falling edge
of the keyboard clock cycle, the Macintosh places the data bit on the dat