;	File:		HardwareEqu.a
;
;	Copyright:	(c) 1983-1993 by Apple Computer, Inc.
;				All rights reserved.
;
;	Version:	System 7.1 for ETO #11
;	Created:	Tuesday, March 30, 1993 18:00
;
;___________________________________________________________________________

	IF &TYPE('__INCLUDINGHARDWAREEQU__') = 'UNDEFINED' THEN
__INCLUDINGHARDWAREEQU__	SET	1


  				IF  		(&TYPE('onMac') = 'UNDEFINED') THEN 
onMac 			EQU 		0
  				ENDIF

  				IF  		(&TYPE('onMacPP') = 'UNDEFINED') THEN
onMacPP   		EQU 		0
  				ENDIF

  				IF  		(&TYPE('onNuMac') = 'UNDEFINED') THEN
onNuMac   		EQU 		0
  				ENDIF

  				IF  		(&TYPE('onHafMac') = 'UNDEFINED') THEN
onHafMac   		EQU 		0
  				ENDIF

  				IF  		(&TYPE('onHcMac') = 'UNDEFINED') THEN
onHcMac   		EQU 		0
  				ENDIF

  				IF  		(&TYPE('onMac16') = 'UNDEFINED') THEN
onMac16   		EQU 		0
  				ENDIF

  				IF  		(&TYPE('onMac32') = 'UNDEFINED') THEN
onMac32   		EQU 		0
  				ENDIF

onAnything		EQU 		onMac|onMacPP|onHcMac|onHafMac|onNuMac


; *** If HWNonPortable is defined to be non-zero, Then a machine type must be specified!
; *** If a machine is specified, HWNonPortable must be non-zero, specified or not.
  				IF  		(&TYPE('HWNonPortable') = 'UNDEFINED') THEN
HWNonPortable 	EQU 		onAnything
  				ENDIF

  				IF  		HWNonPortable THEN

;----------
; Hardware configuration bits.
;----------

;the following goes with hwCfgFlags 

hwCbSCSI  		EQU 		15        				; SCSI port present
hwCbClock 		EQU 		14        				; New clock chip present
hwCbExPRAM		EQU 		13        				; Extra Parameter Ram valid.
hwCbFPU   		EQU 		12        				; FPU chip present.
hwCbMMU   		EQU 		11        				; Some kind of MMU present (see MMUType for what kind).
hwCbADB   		EQU 		10        				; Apple Desktop Bus present.
hwCbAUX			EQU			9						; Running A/UX					<2.8>
hwCbPwrMgr		EQU			8						; Power Manager present			<2.8>
hwCmSCSI  		EQU 		(1 << hwCbSCSI)
hwCmClock 		EQU 		(1 << hwCbClock)
hwCmExPRAM		EQU 		(1 << hwCbExPRAM)
hwCmFPU   		EQU 		(1 << hwCbFPU)
hwCmMMU   		EQU 		(1 << hwCbMMU)
hwCmADB   		EQU 		(1 << hwCbADB)
hwCmAUX			EQU			(1 << hwCbAUX)
hwCmPwrMgr		EQU			(1 << hwCbPwrMgr)



;----------
; 6522 VIA offsets
;----------

vBufB 			EQU 		0 						; BUFFER B
vBufAH			EQU 		$200  					; buffer a (with handshake) [ Dont use! ]
vDIRB 			EQU 		$400  					; DIRECTION B
vDIRA 			EQU 		$600  					; DIRECTION A
vT1C  			EQU 		$800  					; TIMER 1 COUNTER (L.O.)
vT1CH 			EQU 		$A00  					; timer 1 counter (high order)
vT1L  			EQU 		$C00  					; TIMER 1 LATCH (L.O.)
vT1LH 			EQU 		$E00  					; timer 1 latch (high order)
vT2C  			EQU 		$1000 					; TIMER 2 LATCH (L.O.)
vT2CH 			EQU 		$1200 					; timer 2 counter (high order)
vSR   			EQU 		$1400 					; SHIFT REGISTER
vACR  			EQU 		$1600 					; AUX. CONTROL REG.
vPCR  			EQU 		$1800 					; PERIPH. CONTROL REG.
vIFR  			EQU 		$1A00 					; INT. FLAG REG.
vIER  			EQU 		$1C00 					; INT. ENABLE REG.
vBufA 			EQU 		$1E00 					; BUFFER A

; === VIA IFR/IER bits ===
ifCA2 			EQU 		0 						; CA2 interrupt
ifCA1 			EQU 		1 						; CA1 interrupt
ifSR  			EQU 		2 						; SR shift register done
ifCB2 			EQU 		3 						; CB2 interrupt
ifCB1 			EQU 		4 						; CB1 interrupt
ifT2  			EQU 		5 						; T2 timer2 interrupt
ifT1  			EQU 		6 						; T1 timer1 interrupt
ifIRQ 			EQU 		7 						; any interrupt


;----------
; IWM Offsets
;----------

ph0L  			EQU 		0 						; disk address offsets from base
ph0H  			EQU 		$200
ph1L  			EQU 		$400
ph1H  			EQU 		$600
ph2L  			EQU 		$800
ph2H  			EQU 		$A00
ph3L  			EQU 		$C00
ph3H  			EQU 		$E00
mtrOff			EQU 		$1000
mtrOn 			EQU 		$1200
intDrive  		EQU 		$1400 					; enable internal drive address
extDrive  		EQU 		$1600 					; enable external drive address
q6L   			EQU 		$1800
q6H   			EQU 		$1A00
q7L   			EQU 		$1C00
q7H   			EQU 		$1E00

;_______________________________________;			<2.5>
;
;  SWIM offsets
;_______________________________________;

wData 			EQU 		$0000 					;Write a data byte
wMark 			EQU 		$0200 					;Write a mark byte
wCRC  			EQU 		$0400 					;Write a 2-byte CRC (1 access does both)
wIWMConfig		EQU 		wCRC  					;Set IWM configuration
wParams   		EQU 		$0600 					;Set the 16 parameter registers
wPhase			EQU 		$0800 					;Set phase lines states and directions
wSetup			EQU 		$0A00 					;Set the current configuration
wZeroes   		EQU 		$0C00 					;Mode reg: 1's clr bits, 0's=don't care
wOnes 			EQU 		$0E00 					;Mode reg: 1's set bits, 0's=don't care
rData 			EQU 		$1000 					;Read a data byte
rCorrection   	EQU 		rData 					;Read the correction factor
rMark 			EQU 		$1200 					;Read a mark byte
rError			EQU 		$1400 					;Error register
rParams   		EQU 		$1600 					;Parameters (16 bytes deep at this addr)
rPhase			EQU 		$1800 					;Phase lines states and directions
rSetup			EQU 		$1A00 					;Read the current configuration
rStatus   		EQU 		$1C00 					;Status (returns current mode reg value)
rHandshake		EQU 		$1E00 					;Handshake register


;----------
; 8530 SCC Offsets
;----------

aData 			EQU 		6 						; offset for A channel data
aCtl  			EQU 		2 						; offset for A channel control
bData 			EQU 		4 						; offset for B channel data
bCtl  			EQU 		0 						; offset for B channel control
sccData   		EQU 		4 						; general offset for data from control
rxBF  			EQU 		0 						; SCC receive buffer full
txBE  			EQU 		2 						; SCC transmit buffer empty
RxCA			EQU			0						; Receive Character Available			<5>

;----------
; SCC Clock Rates, Baud Rate Constants
;----------

macClock  		EQU 		36707 					; in Hz * 100
hcMacClock		EQU 		36720 					; SCC clock rates
midMacClock   	EQU 		39168
nuMacClock		EQU 		36864
lisaAClock		EQU 		40000 					; port A clock
lisaBCLock		EQU 		36864 					; port B clock
macConst  		EQU 		114709    				; in Hz/32
hcMacConst		EQU 		114750
midMacConst   	EQU 		122400
nuMacConst		EQU 		115200
lisaAConst		EQU 		125000
lisaBConst		EQU 		115200


;----------
; 53C80 SCSI Register Defs, Offsets
;----------

sCDR  			EQU 		$00   					; Current SCSI Read Data
sODR  			EQU 		$00   					; Output data register
sICR  			EQU 		$10   					; Initiator Command Register - READ/WRITE
iRST  			EQU 		$80   					; *RST asserted
iAIP  			EQU 		$40   					; arbitration in progress (read)
bAIP  			EQU 		6 						; bit test for arbitration in progress
aTMD  			EQU 		$40   					; assert Test Mode (write)
iLA   			EQU 		$20   					; Lost arbitration (read)
bLA   			EQU 		5 						; bit test for Lost Arbitration
aDIFF 			EQU 		$20   					; assert Differential enable (write)
iACK  			EQU 		$10   					; *ACK is asserted
iBSY  			EQU 		$08   					; *BSY is asserted
iSEL  			EQU 		$04   					; *SEL is asserted
iATN  			EQU 		$02   					; *ATN is asserted
iDB   			EQU 		$01   					; Data bus is asserted
sMR   			EQU 		$20   					; Mode Register - READ/WRITE
iBDMA 			EQU 		$80   					; Block Mode DMA
iTGT  			EQU 		$40   					; Target Mode
iPTY  			EQU 		$20   					; Enable Parity Checking
iIPTY 			EQU 		$10   					; Enable Parity interrupt
iIEOP 			EQU 		$08   					; Enable EOP interrupt
iMBSY 			EQU 		$04   					; Monitor BSY
iDMA  			EQU 		$02   					; DMA Mode
iARB  			EQU 		$01   					; Arbitration
sTCR  			EQU 		$30   					; Target Command Register - READ/WRITE
iREQ  			EQU 		$08   					; Assert *REQ
iMSG  			EQU 		$04   					; Assert *MSG
iCD   			EQU 		$02   					; Assert C/*D
iIO   			EQU 		$01   					; Assert I/*O
sCSR  			EQU 		$40   					; Current SCSI Bus Status (READ)
aRST  			EQU 		$80   					; *RST
aBSY  			EQU 		$40   					; *BSY
bBSY  			EQU 		6 						; bit test for *BSY
aREQ  			EQU 		$20   					; *REQ
bREQ  			EQU 		5 						; bit test for *REQ
aMSG  			EQU 		$10   					; *MSG
bMSG  			EQU 		4 						; bit test for *MSG
aCD   			EQU 		$08   					; C/*D
bCD   			EQU 		3 						; bit test for C/*D
aIO   			EQU 		$04   					; I/*O
bIO   			EQU 		2 						; bit test for I/*O
aSEL  			EQU 		$02   					; *SEL
bSEL  			EQU 		1 						; bit test for *SEL
aDBP  			EQU 		$01   					; *DBP
sSER  			EQU 		$40   					; Select Enable Register (WRITE)
sBSR  			EQU 		$50   					; Bus & Status Register (READ)
iEDMA 			EQU 		$80   					; End of DMA
bEDMA 			EQU 		7 						; bit test for end of DMA
iDMAR 			EQU 		$40   					; DMA Request
bDMAR 			EQU 		6 						; bit test for DMA Req
iPERR 			EQU 		$20   					; Parity Error
iIREQ 			EQU 		$10   					; Interrupt Request
bIREQ 			EQU 		4 						; bit test for interrupt
iPM   			EQU 		$08   					; Phase Match
bPM   			EQU 		3 						; bit test for Phase Match
iBERR 			EQU 		$04   					; Bus Error
ATN   			EQU 		$02   					; *ATN
ACK   			EQU 		$01   					; *ACK
bACK  			EQU 		0 						; bit test for ACK
sDMAtx			EQU 		$50   					; DMA Transmit Start (WRITE)
sIDR  			EQU 		$60   					; Data input register (READ)
sTDMArx   		EQU 		$60   					; Start Target DMA receive (WRITE)
sRESET			EQU 		$70   					; Reset Parity/Interrupt (READ)
sIDMArx   		EQU 		$70   					; Start Initiator DMA receive (WRITE)



;----------
; VIA2 register definitions
;----------

; === VIA2 BUFFER A ===
v2IRQ1			EQU 		0 						; slot 1 interrupt
v2IRQ2			EQU 		1 						; slot 2 interrupt
v2IRQ3			EQU 		2 						; slot 3 interrupt
v2IRQ4			EQU 		3 						; slot 4 interrupt
v2IRQ5			EQU 		4 						; slot 5 interrupt
v2IRQ6			EQU 		5 						; slot 6 interrupt
v2RAM0			EQU 		6 						; RAM size bit 0
v2RAM1			EQU 		7 						; RAM size bit 1

; === VIA2 BUFFER B ===
v2CDis			EQU 		0 						; cache disable (when 1)	<3.3>
v2BusLk   		EQU 		1 						; Bus lockout
v2PowerOff		EQU 		2 						; soft power off signal (when 0)
vFC3  			EQU 		3 						; PMMU FC3 indicator
v2TM1A			EQU 		4 						; bit for NUBus
v2TM0A			EQU 		5 						; and another
v2SndExt  		EQU 		6 						; 1 = internal speaker, 0 = ext. audio
v2VBL 			EQU 		7 						; pseudo VBL signal


  				IF  		onMac THEN
;=======================================;
;  Macintosh Plus Hardware Information	;
;=======================================;

hwCfgBits 		EQU 		hwCmSCSI++hwCmClock
machine   		EQU 		0
rom85Bits 		EQU 		$7F   					; New ROMs, No Power Off.

; === Interrupt Masks ===
hiIntMask 		EQU 		$0300					; programmer switch only
sccIntMask		EQU 		$0200 					; SCC interrupt Level		<1.5>
sccEnblMask   	EQU 		$F9FF 					; mask to enable SCC interrupts
viaIntMask		EQU 		$0100 					; mask for VIA (and VBL) interrupts
loIntMask 		EQU 		$0100

; === VIA1 BUFFER A ===
vSound			EQU 		$7    					; sound volume bits (0..2)
vSndPg2   		EQU 		3 						; select sound page 2 if 0
vOverlay  		EQU 		4 						; overlay bit (overlay when 1)
vHeadSel  		EQU 		5 						; head select line for Sony
vPage2			EQU 		6 						; select video page 2 if 0
vSCCWrReq 		EQU 		7 						; SCC write/request line

vAOut 			EQU 		(vSound)|\				; sound volume bits are outputs
							(1<<vSndPg2)|\			; sound page 2 select is an output
							(1<<vOverlay)|\			; overlay bit is an output
							(1<<vHeadSel)|\			; head select line is an output
							(1<<vPage2)|\			; video page 2 select is an output
							(0<<vSCCWrReq)			; SCC write/request line is an input

vAInit 			EQU 		(1)|\					; sound volume level initially 1
							(1<<vSndPg2)|\			; main sound buffer selected
							(0<<vOverlay)|\			; overlay is turned off
							(1<<vHeadSel)|\			; head select line is an output
							(1<<vPage2)|\			; main screen buffer selected
							(0<<vSCCWrReq)			; SCC write/request line is an input

vBufD 			EQU 		vBufA 					; disk head select is buffer A


; === VIA1 BUFFER B ===
vRTCData  		EQU 		0 						; real time clock data
vRTCClk   		EQU 		1 						; real time clock clock pulses
vRTCEnb   		EQU 		2 						; clock enable (0 for enable)
vSW   			EQU 		3 						; mouse switch (0 when down)
vX2   			EQU 		4 						; mouse X level
vY2   			EQU 		5 						; mouse Y level
vH4   			EQU 		6 						; horizontal sync
vSndEnb   		EQU 		7 						; /sound enable (reset when 1)

vBOut 			EQU 		(1<<vRTCData)|\			; real time clock data initially an output
							(1<<vRTCClk)|\			; real time clock clock is an output
							(1<<vRTCEnb)|\			; clock enable is an output
							(0<<vSW)|\				; mouse switch is an input
							(0<<vX2)|\				; mouse X level is an input
							(0<<vY2)|\				; mouse Y level is an input
							(0<<vH4)|\				; horizontal sync is an input
							(1<<vSndEnb)			; sound enable is an output

vBInit 			EQU 		(1<<vRTCData)|\			; real time clock data is one
							(1<<vRTCClk)|\			; real time clock clock is high
							(1<<vRTCEnb)|\			; clock initially disabled
							(0<<vSW)|\				; mouse switch is an input
							(0<<vX2)|\				; mouse X level is an input
							(0<<vY2)|\				; mouse Y level is an input
							(0<<vH4)|\				; horizontal sync is an input
							(1<<vSndEnb)			; sound is disabled

vBufM			EQU 		vBufB  					; mouse state is buffer B


; === Hardware Base Addresses ===

PhaseRead 		EQU 		$F00000   				; Phase read address

VBase 			EQU 		$EFE1FE   				; VIA base address
AVBufA			EQU 		VBase+vBufA 			; VIA buffer A
AVBufB			EQU 		VBase+vBufB  			; VIA buffer B
AVBufM			EQU 		VBase+vBufM  			; VIA buffer with mouse button bit

SCCRBase  		EQU 		$9FFFF8   				; SCC base read address
SCCWBase  		EQU 		$BFFFF9   				; SCC base write address
sccWrite  		EQU 		SCCWBase-SCCRBase		; general offset for write from read

SCSIRd			EQU 		$580000   				; base addr SCSI interface - READ
SCSIWr			EQU 		$580001   				; base addr SCSI interface - WRITE
wrOffs			EQU 		SCSIWr-SCSIRd			; write addrs are +1 to the read base

SoundLow  		EQU 		$3FFD00   				; sound buffer start address
snd2MemTop		EQU 		$300  					; SoundLow to Memtop

PWMBuffer 		EQU 		$3FFD01   				; PWM bytes are low bytes
pwm2MemTop		EQU 		$2FF  					; PWMBuffer to MemTop

; === Video Parameters ===

ScreenLow 		EQU 		$3FA700   				; top of screen screen address
scrn2MemTop   	EQU 		$5900 					; ScreenBase to Memtop

; === System Software Information ===

bufWorldSize  	EQU 		scrn2MemTop   			; total size of the BufPtr world
seRegs			EQU 		$3FFC80   				; Sys Error Regs w/o Overlay

  				ELSEIF  	onMacPP THEN
;=======================================;
;	Macintosh SE Hardware Information	;
;=======================================;

hwCfgBits 		EQU 		hwCmSCSI++hwCmClock++hwCmADB
machine   		EQU 		2
rom85Bits 		EQU 		$7F   					; New ROMs, No Power Off.

; === Interrupt Masks ===
hiIntMask 		EQU 		$0300					; programmer switch only
sccIntMask		EQU 		$0200 					; SCC interrupt Level		<1.5>
sccEnblMask   	EQU 		$F9FF 					; mask to enable SCC interrupts
viaIntMask		EQU 		$0100 					; mask for VIA (and VBL) interrupts
loIntMask 		EQU 		$0100

; === VIA1 BUFFER A ===
vSound			EQU 		$7    					; sound volume bits (0..2)
vSync 			EQU 		3 						; Synchronous modem
vDriveSel 		EQU 		4 						; int drive select (lower drive when 1)
vHeadSel  		EQU 		5 						; head select line for Sony
vPage2			EQU 		6 						; select video page 2 if 0
vSCCWrReq 		EQU 		7 						; SCC write/request line

vAOut 			EQU 		(vSound)|\				; sound volume bits are outputs
							(1<<vSync)|\			; Synchronous modem is an output
							(1<<vDriveSel)|\		; int drive select is an output
							(1<<vHeadSel)|\			; head select line is an output
							(1<<vPage2)|\			; video page 2 select is an output
							(0<<vSCCWrReq)			; SCC write/request line is an input

vAInit 			EQU 		(1)|\					; sound volume level initially 1
							(1<<vSync)|\			; Synchronous modem disabled (active low)
							(0<<vDriveSel)|\		; upper floppy drive selected
							(1<<vHeadSel)|\			; head select line is an output
							(1<<vPage2)|\			; main screen buffer selected
							(0<<vSCCWrReq)			; SCC write/request line is an input

vBufD 			EQU 		vBufA 					; disk head select is buffer A


; === VIA1 BUFFER B ===
vRTCData  		EQU 		0 						; real time clock data
vRTCClk   		EQU 		1 						; real time clock clock pulses
vRTCEnb   		EQU 		2 						; clock enable (0 for enable)
vFDBInt   		EQU 		3 						; Front Desk bus interrupt
vFDesk1   		EQU 		4 						; Front Desk bus state bit 0
vFDesk2   		EQU 		5 						; Front Desk bus state bit 1
vSCSIMask 		EQU 		6 						; SCSI IRQ mask
vH4   			EQU 		vSCSIMask				; SCSI IRQ mask (was horiz. sync)
vSndEnb   		EQU 		7 						; /sound enable (reset when 1)

vBOut 			EQU 		(1<<vRTCData)|\			; real time clock data initially an output
							(1<<vRTCClk)|\			; real time clock clock is an output
							(1<<vRTCEnb)|\			; clock enable is an output
							(0<<vFDBInt)|\			; Front Desk bus interrupt is an input
							(1<<vFDesk1)|\			; FDB state bit 0 is an output
							(1<<vFDesk2)|\			; FDB state bit 1 is an output
							(1<<vSCSIMask)|\		; SCSI IRQ mask is an output
							(1<<vSndEnb)			; sound enable is an output

vBInit 			EQU 		(1<<vRTCData)|\			; real time clock data is one
							(1<<vRTCClk)|\			; real time clock clock is high
							(1<<vRTCEnb)|\			; clock initially disabled
							(0<<vFDBInt)|\			; Front Desk bus interrupt is an input
							(1<<vFDesk1)|\			; FDB state bit 0 is initially state 3
							(1<<vFDesk2)|\			; FDB state bit 1 is initially state 3
							(1<<vSCSIMask)|\		; SCSI IRQ mask is initially masked
							(1<<vSndEnb)			; sound is disabled


; === Hardware Base Addresses ===

VBase 			EQU 		$EFE1FE   				; VIA base address
AVBufA			EQU 		VBase+vBufA 			; VIA buffer A
AVBufB			EQU 		VBase+vBufB  			; VIA buffer B

SCCRBase  		EQU 		$9FFFF8   				; SCC base read address
SCCWBase  		EQU 		$BFFFF9   				; SCC base write address
sccWrite  		EQU 		SCCWBase-SCCRBase		; general offset for write from read

SCSIRd			EQU 		$5FF000   				; base addr SCSI interface - READ
SCSIWr			EQU 		$5FF001   				; base addr SCSI interface - WRITE
MacSCSIBase   	EQU 		$5FF000   				; base addr SCSI READ interface
MacSCSIDMA		EQU 		$5FF200   				; base addr SCSI DMA
MacSCSIHsk		EQU 		$5FF200   				; base addr SCSI handshake
wrOffs			EQU 		SCSIWr-SCSIRd			; write addrs are +1 to the read base

SoundLow  		EQU 		$3FFD00   				; sound buffer start address
snd2MemTop		EQU 		$300  					; SoundLow to Memtop

PWMBuffer 		EQU 		$3FFD01   				; PWM bytes are low bytes
pwm2MemTop		EQU 		$2FF  					; PWMBuffer to MemTop

; === Video Parameters ===

ScreenLow 		EQU 		$3FA700   				; top of screen screen address
scrn2MemTop   	EQU 		$5900 					; ScreenBase to Memtop

; === System Software Information ===

bufWorldSize  	EQU 		scrn2MemTop   			; total size of the BufPtr world
seRegs			EQU 		$3FFC80   				; Sys Error Regs w/o Overlay

  				ELSEIF  	onHcMac THEN
;===========================================;
;	Macintosh Portable Hardware Information	;
;===========================================;

hwCfgBits 		EQU 		hwCmSCSI++hwCmClock++hwCmADB++hwCbPwrMgr				; <2.8>
machine   		EQU 		3
rom85Bits 		EQU 		$7F   					; New ROMs, No Power Off.

; === Interrupt Masks ===
hiIntMask 		EQU 		$0300					; programmer switch only
sccIntMask		EQU 		$0200 					; SCC interrupt Level		<1.5>
sccEnblMask   	EQU 		$F9FF 					; mask to enable SCC interrupts
viaIntMask		EQU 		$0100 					; mask for VIA (and VBL) interrupts
loIntMask 		EQU 		$0100

; === VIA1 BUFFER A ===
													; 68000 <-> PowerMgr data bus
vAIn  			EQU 		$00   					; VBufA output bits (all inputs)
vAOut 			EQU 		$FF   					; VBufA output bits (all outputs)
vAInit			EQU 		$00   					; VBufA initial values


; === VIA1 BUFFER B ===
vPMreq			EQU 		0 						; Power manager handshake request
vPMack			EQU 		1 						; Power manager handshake acknowledge
vTestJ			EQU 		2 						; Test jumper
vSync 			EQU 		3 						; Synchronous modem
vDriveSel 		EQU 		4 						; int drive select (lower drive when 1)
vHeadSel  		EQU 		5 						; head select line for Sony
vStereo   		EQU 		6 						; Stereo sound enable
vSCCWrReq 		EQU 		7 						; SCC write/request line		(input)
vSndEnb   		EQU 		7 						; /sound enable (reset when 1)	(output)

vBOut 			EQU 		(1<<vPMreq)|\			; Power mgr handshake request is an output
							(0<<vPMack)|\			; Power mgr handshake acknowledge is an input
							(0<<vTestJ)|\			; Test jumper is an input
							(1<<vSync)|\			; Synchronous modem is an output
							(1<<vDriveSel)|\		; int drive select is an output
							(1<<vHeadSel)|\			; head select line is an output
							(0<<vStereo)|\			; Stereo sound detect is an input
							(1<<vSndEnb)			; sound enable is an output

vBInit 			EQU 		(1<<vPMreq)|\			; Power mgr handshake not requesting
							(1<<vPMack)|\			; Power mgr handshake acknowledge is an input
							(1<<vTestJ)|\			; Test jumper is an input
							(1<<vSync)|\			; Synchronous modem disabled (active low)
							(1<<vDriveSel)|\		; lower floppy drive selected
							(0<<vHeadSel)|\			; head select line is an output
							(1<<vStereo)|\			; Stereo sound detect is an input
							(1<<vSndEnb)			; sound is disabled

vBufD 			EQU 		vBufB 					; disk head select is buffer B


; === Hardware Base Addresses ===

VBase 			EQU 		$F70000   				; VIA base address
AVBufA			EQU 		VBase+vBufA 			; VIA buffer A
AVBufB			EQU 		VBase+vBufB  			; VIA buffer B

SCCRBase  		EQU 		$FD0000   				; SCC base read address
SCCWBase  		EQU 		$FD8000   				; SCC base write address
sccWrite  		EQU 		SCCWBase-SCCRBase		; general offset for write from read

SCSIRd			EQU 		$F90000   				; base address of SCSI interface - READ
SCSIWr			EQU 		$F90001   				; base address of SCSI interface - WRITE
MacSCSIBase   	EQU 		$F90000   				; base address of SCSI READ interface
MacSCSIDMA		EQU 		$F90200   				; base address of SCSI DMA
MacSCSIHsk		EQU 		$F90200   				; base address of SCSI handshake
wrOffs			EQU 		SCSIWr-SCSIRd			; write addrs are +1 to the read base

SndBase   		EQU 		$FB0000   				; sound chip's base address

MapperBase		EQU 		$FC0000   				; Mapper RAM base address

RAMconfigBase 	EQU 		$FE0200   				; Internal/external RAM control register
RAMconfigInit	EQU			$0006					; Init test register						<v2.6>

; === Video Parameters ===

ScreenLow 		EQU 		$FA8000   				; top of screen screen address
hcVideoSize   	EQU 		$8000 					; 32k of video memory
HcVideoStart  	EQU 		ScreenLow
HcVideoEnd		EQU 		HcVideoStart+hcVideoSize
NTSCMaxX		EQU			512						; NTSC output is narrow
NTSCOffset		EQU			8						;  and centered
LCDmode			EQU			0						; Normal built in screen
Mac2mode		EQU			1						; Custom screen for Mac2
NTSCmode		EQU			2						; NTSC output

; === System Software Information ===
snd2MemTop		EQU 		$300  					; SoundLow to Memtop
pwm2MemTop		EQU 		$2FF  					; PWMBuffer to MemTop
bufWorldSize  	EQU 		snd2MemTop    			; total size of the BufPtr world
seRegs			EQU 		$0C30 					; offset to Sys Error Regs w/o Overlay


  				ELSEIF  	onMac16 THEN
;===================================================;
;	Universal 16 bit Macintosh Hardware Information	;
;===================================================;


; === Interrupt Masks ===
hiIntMask 		EQU 		$0300					; programmer switch only
sccIntMask		EQU 		$0200 					; SCC interrupt Level		<1.5>
sccEnblMask   	EQU 		$F9FF 					; mask to enable SCC interrupts
viaIntMask		EQU 		$0100 					; mask for VIA (and VBL) interrupts
loIntMask 		EQU 		$0100

; === VIA1 BUFFER A ===
vSound			EQU 		$7    					; sound volume bits (0..2)
vSndPg2   		EQU 		3 						; select sound page 2 if 0
;vSync 			EQU 		3 						; Synchronous modem
vOverlay  		EQU 		4 						; overlay bit (overlay when 1)
;vDriveSel 		EQU 		4 						; int drive select (lower drive when 1)
;vHeadSel  		EQU 		5 						; head select line for Sony
vPage2			EQU 		6 						; select video page 2 if 0
;vSCCWrReq 		EQU 		7 						; SCC write/request line


; === VIA1 BUFFER B ===
vRTCData  		EQU 		0 						; real time clock data
vRTCClk   		EQU 		1 						; real time clock clock pulses
vRTCEnb   		EQU 		2 						; clock enable (0 for enable)
vSW   			EQU 		3 						; mouse switch (0 when down)
vFDBInt   		EQU 		3 						; Front Desk bus interrupt
vX2   			EQU 		4 						; mouse X level
vFDesk1   		EQU 		4 						; Front Desk bus state bit 0
vY2   			EQU 		5 						; mouse Y level
vFDesk2   		EQU 		5 						; Front Desk bus state bit 1
vH4   			EQU 		6 						; horizontal sync
vSCSIMask 		EQU 		6 						; SCSI IRQ mask
vSndEnb   		EQU 		7 						; /sound enable (reset when 1)

vPMreq			EQU 		0 						; Power manager handshake request
vPMack			EQU 		1 						; Power manager handshake acknowledge
vTestJ			EQU 		2 						; Test jumper
;vSync 			EQU 		3 						; Synchronous modem
;vDriveSel 		EQU 		4 						; int drive select (lower drive when 1)
;vHeadSel  		EQU 		5 						; head select line for Sony
vStereo   		EQU 		6 						; Stereo sound enable
;vSCCWrReq 		EQU 		7 						; SCC write/request line		(input)

; === VIA1 BUFFER A/B ===
vSync 			EQU 		3 						; Synchronous modem						<3.1>
vDriveSel 		EQU 		4 						; int drive select (lower drive when 1)	<3.1>
vHeadSel  		EQU 		5 						; head select line for Sony				<3.1>
vSCCWrReq 		EQU 		7 						; SCC write/request line				<3.1>

; === Hardware Base Addresses ===

wrOffs			EQU 		1						; write addrs are +1 to the read base

; === System Software Information ===
seRegs			EQU 		$0C30 					; offset to Sys Error Regs w/o Overlay

  				ELSEIF  	onMac32 THEN
;===================================================;
;	Universal 32 bit Macintosh Hardware Information	;
;===================================================;

machine   		EQU 		6						; for patch file $067C					<3.5>

; === Interrupt Masks ===
hiIntMask 		EQU 		$0700					; programmer switch only
pwrOffEnbl		EQU 		$2500					; mask to allow poweroff interrupts
sccIntMask		EQU 		$0400					; SCC interrupt level
sccEnblMask   	EQU 		$FBFF					; mask to enable SCC interrupts
slotIntMask   	EQU 		$0200		   			; slot's interrupt level	<v1.4><1.9>
viaIntMask		EQU 		$0100					; VIA1 interrupt level
loIntMask 		EQU 		$0100

; === VIA1 BUFFER A ===
vSound			EQU 		$7    					; sound volume bits (0..2)	(output)
vTestJ			EQU 		0 						; Burn In Test jumper		(input)
vCpuId0			EQU			1						; CPU Identification bit 0	(input)
vCpuId1			EQU			2						; CPU Identification bit 1	(input)
vSync 			EQU 		3 						; Synchronous modem
vOverlay  		EQU 		4 						; overlay bit (overlay when 1)
vCpuId2			EQU			4						; CPU Identification bit 2
vHeadSel  		EQU 		5 						; head select line for Sony
vRev8Bd   		EQU 		6 						; =0 for rev 8 board
vCpuId3			EQU			6						; CPU Identification bit 3
vSCCWrReq 		EQU 		7 						; SCC write/request line

; === VIA1 BUFFER B ===
vRTCData  		EQU 		0 						; real time clock data
v0reserved		EQU			0						; reserved bit in Erickson				<6>
vRTCClk   		EQU 		1 						; real time clock clock pulses
v1reserved		EQU			1						; reserved bit in Erickson				<6>
vRTCEnb   		EQU 		2 						; clock enable (0 for enable)
v2reserved		EQU			2						; reserved bit in Erickson				<6>
vFDBInt   		EQU 		3 						; Front Desk bus interrupt
xcvrsesbit		EQU			3						; Egret transceiver session bit			<6>
vFDesk1   		EQU 		4 						; Front Desk bus state bit 0
viafullbit		EQU			4						; Egret via full bit					<6>
vFDesk2   		EQU 		5 						; Front Desk bus state bit 1
syssesbit		EQU			5						; Egret system session bit				<6>
vPGCEnb			EQU			6						; Parity Generator/Checker enable (0 for enable)
v6reserved		EQU			6						; reserved bit in Erickson				<6>
vPGCErr			EQU			7						; Parity Generator/Checker error	(input)
v7reserved		EQU			7						; reserved bit in Erickson				<6>
vSndEnb   		EQU 		7 						; /sound enable (reset when 1)		(output)


; === Hardware Base Addresses ===

WrOffs			EQU			0						; SCSI write addrs are same as read base

MskIOP1			EQU			1						; IOP 1 (SWIM) is level 1 interrupt
MskVIA1			EQU			1						; VIA 1 is level 1
MskADB			EQU			1						; ADB is level 1
Msk60Hz			EQU			1						; 60 Hz is level 1
MskSCSI			EQU			2						; SCSI is level 2
MskSound		EQU			2						; sound is level 2						<4.5>
MskSlots		EQU			2						; slots are level 2 interrupts
MskRTC			EQU			3						; RTC is level 3
MskIOP0			EQU			4						; IOP 0 (& SCC chip) is level 4
MskPwrOff		EQU			6						; Poweroff button is level 6
MskNMI			EQU			7						; NMI switch is level 7

; === System Software Information ===
snd2MemTop		EQU 		$300  					; SoundLow to Memtop
pwm2MemTop		EQU 		$2FF  					; PWMBuffer to MemTop
bufWorldSize  	EQU 		snd2MemTop    			; total size of the BufPtr world
seRegs			EQU 		$0C30 					; offset to Sys Error Regs w/o Overlay


  				ELSEIF  	onHafMac THEN
;===================================;
;	Mac IIci Hardware Information	;
;===================================;

machine   		EQU 		6

; === Interrupt Masks ===
hiIntMask 		EQU 		$0700 					; programmer switch only
pwrOffEnbl		EQU 		$2500 					; mask to allow poweroff interrupts
sccIntMask		EQU 		$0400 					; SCC interrupt level
sccEnblMask   	EQU 		$FBFF 					; mask to enable SCC interrupts
via2IntMask   	EQU 		$0200 					; VIA2 interrupt level		<v1.4><1.9>
slotIntMask   	EQU 		via2IntMask   			; slot's interrupt level	<v1.4><1.9>
viaIntMask		EQU 		$0100 					; VIA1 interrupt level
loIntMask 		EQU 		$0100

; === VIA1 BUFFER A ===
vSound			EQU 		$7    					; sound volume bits (0..2)	(output)
vTestJ			EQU 		0 						; Burn In Test jumper		(input)
vCpuId0			EQU			1						; CPU Identification bit 0	(input)
vCpuId1			EQU			2						; CPU Identification bit 1	(input)
vSync 			EQU 		3 						; Synchronous modem
vCpuId2			EQU			4						; CPU Identification bit 2
vHeadSel  		EQU 		5 						; head select line for Sony
vCpuId3			EQU			6						; CPU Identification bit 3
vSCCWrReq 		EQU 		7 						; SCC write/request line

vAOut 			EQU 		(vSound)|\				; sound volume bits are outputs
							(1<<vSync)|\			; Synchronous modem is an output
							(0<<vCpuId2)|\			; CPU Identification bit 2 is an input
							(1<<vHeadSel)|\			; head select line is an output
							(0<<vCpuId3)|\			; CPU Identification bit 3 is an input
							(0<<vSCCWrReq)			; SCC write/request line is an input

vAInit 			EQU 		(1)|\					; sound volume level initially 1
							(0<<vSync)|\			; Synchronous modem disabled (active high)
							(0<<vCpuId2)|\			; CPU Identification bit 2 is an input
							(1<<vHeadSel)|\			; head select line is an output
							(0<<vCpuId3)|\			; CPU Identification bit 3 is an input
							(0<<vSCCWrReq)			; SCC write/request line is an input

vBufD 			EQU 		vBufA 					; disk head select is buffer A


; === VIA1 BUFFER B ===
vRTCData  		EQU 		0 						; real time clock data
vRTCClk   		EQU 		1 						; real time clock clock pulses
vRTCEnb   		EQU 		2 						; clock enable (0 for enable)
vFDBInt   		EQU 		3 						; Front Desk bus interrupt
vFDesk1   		EQU 		4 						; Front Desk bus state bit 0
vFDesk2   		EQU 		5 						; Front Desk bus state bit 1
vPGCEnb			EQU			6						; Parity Generator/Checker enable (0 for enable)
vPGCErr			EQU			7						; Parity Generator/Checker error	(input)
vSndEnb   		EQU 		7 						; /sound enable (reset when 1)		(output)

vBOut 			EQU 		(1<<vRTCData)|\			; real time clock data initially an output
							(1<<vRTCClk)|\			; real time clock clock is an output
							(1<<vRTCEnb)|\			; clock enable is an output
							(0<<vFDBInt)|\			; Front Desk bus interrupt is an input
							(1<<vFDesk1)|\			; FDB state bit 0 is an output
							(1<<vFDesk2)|\			; FDB state bit 1 is an output
							(1<<vPGCEnb)|\			; PGC enable is an output
							(1<<vSndEnb)			; sound enable is an output

vBInit 			EQU 		(1<<vRTCData)|\			; real time clock data is one
							(1<<vRTCClk)|\			; real time clock clock is high
							(1<<vRTCEnb)|\			; clock initially disabled
							(0<<vFDBInt)|\			; Front Desk bus interrupt is an input
							(1<<vFDesk1)|\			; FDB state bit 0 is initially state 3
							(1<<vFDesk2)|\			; FDB state bit 1 is initially state 3
							(1<<vPGCEnb)|\			; Parity Checking is initially disabled
							(1<<vSndEnb)			; sound is disabled


; === RBV BUFFER B ===
RvBInit			EQU			(1<<RvCDis)|\			; cache disabled	<3.3>
							(1<<RvBusLk)|\			; Bus unlocked
							(1<<RvPowerOff)|\		; Power on
							(1<<RvCFlush)|\			; don't flush cache
							(0<<RvTM1A)|\			; NuBus timeout bits are inputs
							(0<<RvTM0A)|\			; NuBus timeout bits are inputs
							(0<<RvSndExt)|\			; sound/speaker mode is an input
							(1<<RvPGCTest)			; generate correct parity


; === Hardware Base Addresses ===

VBase 			EQU 		$50F00000   			; VIA base address
AVBufA			EQU 		VBase+vBufA 			; VIA buffer A
AVBufB			EQU 		VBase+vBufB  			; VIA buffer B

SCCRBase  		EQU 		$50F04000   			; SCC base read address
SCCWBase  		EQU 		$50F04000   			; SCC base write address
sccWrite  		EQU 		SCCWBase-SCCRBase		; general offset for write from read

NewSCSIBase   	EQU 		$50F10000 				; rev8 base addr SCSI interface
NewSCSIDMA		EQU 		$50F12000 				; rev8 base addr SCSI DMA (corrected)
NewSCSIHsk		EQU 		$50F06000 				; rev8 base addr SCSI handshake
MacSCSIBase   	EQU 		$50F10000 				; base addr SCSI interface
MacSCSIDMA		EQU 		$50F12000 				; base addr SCSI DMA
MacSCSIHsk		EQU 		$50F06000 				; base addr SCSI handshake
wrOffs			EQU 		0 						; write addrs are same as read base

SndBase			EQU 		$50F14000 				; sound chip's base address

; === Video Parameters ===

RBVBase			EQU			$50F26000				; RBV base address				<v1.4><1.4>
vDACBase		EQU			$50F24000				; base of clut

; === System Software Information ===
snd2MemTop		EQU 		$300  					; SoundLow to Memtop
pwm2MemTop		EQU 		$2FF  					; PWMBuffer to MemTop
bufWorldSize  	EQU 		snd2MemTop    			; total size of the BufPtr world
seRegs			EQU 		$0C30 					; offset to Sys Error Regs w/o Overlay

  				ELSEIF  	onNuMac THEN
;=======================================================;
;	Macintosh II, IIx, IIcx, SE30 Hardware Information	;
;=======================================================;

hwCfgBits 		EQU 		hwCmSCSI++hwCmClock++hwCmFPU++hwCmMMU++hwCmADB
machine   		EQU 		1
rom85Bits 		EQU 		$3F   					; New ROMs, Power Off ability.

; === Interrupt Masks ===
hiIntMask 		EQU 		$0700 					; programmer switch only
pwrOffEnbl		EQU 		$2500 					; mask to allow poweroff interrupts
sccIntMask		EQU 		$0400 					; SCC interrupt level
sccEnblMask   	EQU 		$FBFF 					; mask to enable SCC interrupts
via2IntMask   	EQU 		$0200 					; VIA2 interrupt level		<v1.4><1.9>
slotIntMask   	EQU 		via2IntMask   			; slot's interrupt level	<v1.4><1.9>
viaIntMask		EQU 		$0100 					; VIA1 interrupt level
loIntMask 		EQU 		$0100

; === VIA1 BUFFER A ===
vSound			EQU 		$7    					; sound volume bits (0..2)	(output)
vSync 			EQU 		3 						; Synchronous modem
vOverlay  		EQU 		4 						; overlay bit (overlay when 1)
vHeadSel  		EQU 		5 						; head select line for Sony
vRev8Bd   		EQU 		6 						; =0 for rev 8 board
vSCCWrReq 		EQU 		7 						; SCC write/request line

vAOut 			EQU 		(vSound)|\				; sound volume bits are outputs
							(1<<vSync)|\			; Synchronous modem is an output
							(1<<vOverlay)|\			; overlay bit is an output
							(1<<vHeadSel)|\			; head select line is an output
							(0<<vRev8Bd)|\			; board ID is an input
							(0<<vSCCWrReq)			; SCC write/request line is an input

vAInit 			EQU 		(1)|\					; sound volume level initially 1
							(0<<vSync)|\			; Synchronous modem disabled (active high)
							(0<<vOverlay)|\			; overlay is turned off
							(0<<vHeadSel)|\			; head select line is an output
							(0<<vRev8Bd)|\			; board ID is an input
							(0<<vSCCWrReq)			; SCC write/request line is an input

vBufD 			EQU 		vBufA 					; disk head select is buffer A


; === VIA1 BUFFER B ===
vRTCData  		EQU 		0 						; real time clock data
vRTCClk   		EQU 		1 						; real time clock clock pulses
vRTCEnb   		EQU 		2 						; clock enable (0 for enable)
vFDBInt   		EQU 		3 						; Front Desk bus interrupt
vFDesk1   		EQU 		4 						; Front Desk bus state bit 0
vFDesk2   		EQU 		5 						; Front Desk bus state bit 1
;				EQU			6						; unused
vSndEnb   		EQU 		7 						; /sound enable (reset when 1)		(output)

vBOut 			EQU 		(1<<vRTCData)|\			; real time clock data initially an output
							(1<<vRTCClk)|\			; real time clock clock is an output
							(1<<vRTCEnb)|\			; clock enable is an output
							(0<<vFDBInt)|\			; Front Desk bus interrupt is an input
							(1<<vFDesk1)|\			; FDB state bit 0 is an output
							(1<<vFDesk2)|\			; FDB state bit 1 is an output
							(1<<vSndEnb)			; sound enable is an output

vBInit 			EQU 		(1<<vRTCData)|\			; real time clock data is one
							(1<<vRTCClk)|\			; real time clock clock is high
							(1<<vRTCEnb)|\			; clock initially disabled
							(0<<vFDBInt)|\			; Front Desk bus interrupt is an input
							(1<<vFDesk1)|\			; FDB state bit 0 is initially state 3
							(1<<vFDesk2)|\			; FDB state bit 1 is initially state 3
							(0<<vSndEnb)			; sound is enabled


; === VIA2 BUFFER A ===
v2AOut			EQU 		(0<<v2IRQ1)|\     		; slot 1 interrupt is an input
  				(0<<v2IRQ2)|\ 						; slot 2 interrupt is an input
  				(0<<v2IRQ3)|\ 						; slot 3 interrupt is an input
  				(0<<v2IRQ4)|\ 						; slot 4 interrupt is an input
  				(0<<v2IRQ5)|\ 						; slot 5 interrupt is an input
  				(0<<v2IRQ6)|\ 						; slot 6 interrupt is an input
  				(1<<v2RAM0)|\ 						; ram size bit 0 is an output
  				(1<<v2RAM1)   						; ram size bit 1 is an output

v2AInit			EQU			(0<<v2IRQ1)|\			; slot 1 interrupt is an input
							(0<<v2IRQ2)|\			; slot 2 interrupt is an input
							(0<<v2IRQ3)|\			; slot 3 interrupt is an input
							(0<<v2IRQ4)|\			; slot 4 interrupt is an input
							(0<<v2IRQ5)|\			; slot 5 interrupt is an input
							(0<<v2IRQ6)|\			; slot 6 interrupt is an input
							(0<<v2RAM0)|\			; or ram size bit 0 with 0
							(0<<v2RAM1)				; or ram size bit 1 with 0


; === VIA2 BUFFER B ===
v2BOut			EQU			(0<<v2CDis)|\			; cache disabled	<3.3>
  				(0<<v2BusLk)|\						; Bus unlocked
  				(0<<v2PowerOff)|\ 					; Power on
  				(0<<vFC3)|\   						; don't flush cache
  				(0<<v2TM1A)|\ 						; NuBus timeout bits are inputs
  				(0<<v2TM0A)|\ 						; NuBus timeout bits are inputs
  				(0<<v2SndExt)|\   					; sound/speaker mode is an input
  				(1<<v2VBL)							; 60Hz pseudo VBL output

v2BInit			EQU			(1<<v2CDis)|\			; cache disabled (input when not in use)	<3.3>
							(0<<v2BusLk)|\			; Bus unlocked	(input when not in use)
							(1<<v2PowerOff)|\		; Power on	(input when not in use)
							(0<<vFC3)|\				; don't flush cache	(input when not in use)
							(0<<v2TM1A)|\			; NuBus timeout bits are inputs
							(0<<v2TM0A)|\			; NuBus timeout bits are inputs
							(0<<v2SndExt)|\			; sound/speaker mode is an input
							(0<<v2VBL)				; 60Hz pseudo VBL output


; === Hardware Base Addresses ===

VBase 			EQU 		$50F00000     			; VIA base address
AVBufA			EQU 		VBase+vBufA       		; VIA buffer A
AVBufB			EQU 		VBase+vBufB       		; VIA buffer B

VBase2			EQU 		$50F02000 				; VIA2 base address				<v1.4>

SCCRBase  		EQU 		$50F04000     			; SCC base read address
SCCWBase  		EQU 		$50F04000     			; SCC base write address
sccWrite  		EQU 		SCCWBase-SCCRBase     	; general offset for write from read

NewSCSIBase   	EQU 		$50F10000     			; rev8 base addr SCSI interface
NewSCSIDMA		EQU 		$50F12000     			; rev8 base addr SCSI DMA (corrected)
NewSCSIHsk		EQU 		$50F06000     			; rev8 base addr SCSI handshake
MacSCSIBase   	EQU 		$50F10000     			; base addr SCSI interface
MacSCSIDMA		EQU 		$50F12000     			; base addr SCSI DMA
MacSCSIHsk		EQU 		$50F06000     			; base addr SCSI handshake
wrOffs			EQU 		0 						; write addrs are same as read base

SndBase   		EQU 		$50F14000     			; sound chip's base address

; === System Software Information ===
snd2MemTop		EQU 		$300  					; SoundLow to Memtop
pwm2MemTop		EQU 		$2FF  					; PWMBuffer to MemTop
bufWorldSize  	EQU 		snd2MemTop    			; total size of the BufPtr world
seRegs			EQU 		$0C30 					; offset to Sys Error Regs w/o Overlay

  				ENDIF


;----------
; Deep Shit Rectangle info
;----------

dsRectTL  		EQU 		(64<<16)+32       		; top left = 64,32
dsRectBR  		EQU 		(190<<16)+480     		; bottom right = 190,480
dsRectHei 		EQU 		(dsRectBR**$FFFF0000)-(dsRectTL**$FFFF0000)>>16
dsRectLen 		EQU 		(dsRectBR**$FFFF)-(dsRectTL**$FFFF)


  				IF  		onAnything THEN

;----------
; System Error, ROM Based Debugger Nub, MicroBug Equates
;----------

seVars			EQU 		seRegs        			; start of system error data space (wrap city)
seVSize   		EQU 		128       				; # of bytes in space
seD0  			EQU 		seVars        			; loc of saved reg D0
seA0  			EQU 		seD0+32       			; loc of saved reg A0
seA7  			EQU 		seA0+28       			; loc of saved reg A7
sePC  			EQU 		seA7+4        			; loc of saved PC
seSR  			EQU 		sePC+4        			; loc of saved SR
seAccess  		EQU 		seSR+2        			; PC address during bus/address error
seCmdSize 		EQU 		seAccess+4    			; # of bytes of parameters passed in _debugger call
se000BE   		EQU 		seCmdSize+2       		; 8 bytes of bus error info for 68000
seLastVar 		EQU 		se000BE+8     			; last var in System Error data space


;-----
; ROM based debugger nub
;-----

rdPort			EQU 		seLastVar     			; Number of port currently in use (0 => no link, 1 => A, 2 => B)
rdCode			EQU 		rdPort+2      			; Ptr to code download buffer.
rdAtrap   		EQU 		rdCode+4      			; Saved Rom Atrap handler
rdLowTrap 		EQU 		rdAtrap+4     			; low value for trap handling
rdHiTrap  		EQU 		rdLowTrap+2       		; high value for trap handling
rdResult  		EQU 		rdHiTrap+2    			; result of executing down-loaded code, etc. (16 bytes)
rdEnd 			EQU 		rdResult+16       		; end of vars


;-----
; Microbug
;-----

; NOTE: Keep mbDotAddr immediately before mBlocAddr

mbBufSize 		EQU 		34
mbBuffer  		EQU 		seLastVar     			; buffer for input
mbSign			EQU 		mbBuffer+mbBufSize    	; ST => negative sign during conversion
mbDotAddr 		EQU 		mbSign+2      			; saved address
mBlocAddr 		EQU 		mbDotAddr+4       		; saved location

;----------
; Timing constants
;----------

VIAClockHz		EQU			783360					; VIA clock rate is 783360 Hz.		<2.8>
nTicks			EQU 		VIAClockHz/1000   		; VIA timer ticks per msec
oneSecTicks   	EQU 		60    					; ticks, of course
TimeSCSIDB		EQU			$0B24					; DBRAs & SCSI access per millisecond <1.9>

ramChk			EQU 		1024      				; Amount of memory tested for stack.

  				ENDIF

  				ENDIF 								; {HWNonPortable}


	ENDIF	; ...already included 
